Coverage-Directed Test Generation

Concept

Coverage-directed test generation is a hardware functional-verification approach in which generation of stimuli or test programs is guided by coverage goals. In the provided evidence, it appears mainly in processor verification, where unguided random instruction generation can repeatedly exercise the same functionality, while coverage-oriented methods are presented as a way to reduce manual constraint tuning and improve the chance of finding bugs.

First seen 5/26/2026

Last seen 6/6/2026

Evidence 5 chunks

Wiki v2

WIKI

Overview

Coverage-directed test generation is a hardware functional-verification concept concerned with generating verification stimuli that improve coverage. In the provided evidence, the concept appears primarily in processor and microprocessor verification, where generated stimuli are often instruction sequences or test programs intended to exercise architecture and microarchitecture events defined by a verification plan.

Verification context

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NEIGHBORHOOD

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RELATIONSHIPS

4 connections

Bayesian Network Test Generation uses → 85% 2e

CDG mechanisms can use Bayesian networks for test generation

Avi Ziv mentions → 90% 1e

Avi Ziv's research interests include coverage-directed test generation

MicroGP ← implements 90% 1e

MicroGP uses genetic programming for CDG

Markov Chain Model uses → 85% 1e

CDG frameworks can use Markov chain models for test generation

LINKED ENTITIES

4 links

Functional Verification application_context The evidence places coverage-directed test generation in the broader context of hardware functional verification and simulation-based microprocessor verification.

test program generation related_method The evidence describes random and model-based test-program generation for functional processor verification, and identifies coverage and bug discovery as quality requirements for generated tests.

Genesys-Pro example_tool_context Genesys-Pro is explicitly described as a second-generation model-based test-program generation tool for functional processor verification.

ProcessorFuzz related_hardware_fuzzing_context ProcessorFuzz is discussed in evidence that contrasts coverage-guided and unguided processor test generation and hardware fuzzing approaches.

CITATIONS

12 sources

12 citations — click to expand

[1] Functional verification is a bottleneck in the hardware design cycle, and simulation-based techniques play a major role in industrial microprocessor verification. [PDF] Genesys-pro: innovations in test program generation for functional ...

[2] Generated processor-verification stimuli are usually test programs that trigger architecture and microarchitecture events defined by a verification plan, and they must satisfy validity and quality requirements. [PDF] Genesys-pro: innovations in test program generation for functional ...

[3] The quality requirement for generated tests is to expand coverage of the target design and increase the probability of bug discovery. [PDF] Genesys-pro: innovations in test program generation for functional ...

[4] Random instruction generators are common in processor verification because they require limited human expertise and scale to large RTL designs. ProcessorFuzz: Processor Fuzzing with Control and

[5] Lack of coverage guidance in random instruction generators can generate repetitive inputs that test the same processor functionality and reduce the chance of finding bugs. ProcessorFuzz: Processor Fuzzing with Control and

[6] Manually adjusting random-generator constraints can target uncovered RTL regions, but increases engineering effort and slows verification. ProcessorFuzz: Processor Fuzzing with Control and

[7] Researchers proposed coverage-directed test generation mechanisms as a response to the limitations of unguided random generation and manual constraint adjustment. ProcessorFuzz: Processor Fuzzing with Control and

[8] IBM's model-based test-program generation separates a generic architecture-independent engine from a model describing the target architecture. [PDF] Genesys-pro: innovations in test program generation for functional ...

[9] Genesys-Pro is a second-generation model-based test-program generation tool for functional processor verification, improving on Genesys with a more expressive test-template language and greater constraint-solving processing power. [PDF] Genesys-pro: innovations in test program generation for functional ...

[10] Hardware-fuzzing approaches that translate hardware designs to software models can use software-fuzzer coverage metrics such as basic-block and edge coverage, but must address hardware/software model equivalence. ProcessorFuzz: Processor Fuzzing with Control and

[11] TheHuzz uses statement, branch, line, and expression coverage metrics extracted with industrial-standard tools, and the evidence states these software-testing metrics are not sufficient for processor verification. ProcessorFuzz: Processor Fuzzing with Control and

[12] Avi Ziv's listed research interests include functional coverage, coverage-directed test generation, and high-level modeling for hardware systems. [PDF] Genesys-pro: innovations in test program generation for functional ...