Model-Based Test Generation

Technique

Model-based test generation is an automated test-generation technique in which a model or input-format specification guides the creation of test cases or processor-level stimuli. Evidence from processor-verification literature identifies model-based approaches as a notable direction that relies on constraint-based specifications to guide generation, with optimizations such as cross-instruction constraint propagation, and notes the significant effort required to provide an input-format specification, motivating alternative model-free techniques such as coverage-guided fuzzing. Other public work applies model-based generation to domain-specific test modeling and web-app regression testing.

First seen 5/25/2026

Last seen 8/1/2026

Evidence 15 chunks

Wiki v5

WIKI

Overview

Model-based test generation is an automated test-generation technique in which a model, input-format specification, or constraint-based description guides the creation of test cases or processor-level stimuli. In the processor-verification literature, model-based test generation is identified as a notable direction that relies on a constraint-based specification to guide the test generation process, in contrast with classical randomized instruction-stream generation. [Model-based definition and motivation]

The technique is also discussed more broadly in software-engineering contexts as a way to support automated test generation with domain-specific concepts. Public SE work describes a framework in which a language expert builds test models using a full (Java) programming language augmented with simple but powerful modeling elements; based on these models, the toolset automatically forms a domain-specific modeling language that domain experts can use to constrain and guide test generation, generate large test sets, target constrained parts of a model, or manually define specific test cases on top of the model. [Domain-specific model guidance]

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NEIGHBORHOOD

3 nodes · 3 edges

graph · Model-Based Test Generation · depth=1

RELATIONSHIPS

12 connections

Verifying Instruction Set Simulators using Coverage-guided Fuzzing ← compares with 90% 4e

The paper discusses model-based test generation as related work and compares it with the proposed CGF approach.

Processor Verification using Symbolic Execution: A RISC-V Case-Study ← mentions 85% 2e

The paper discusses model-based approaches as related work for test generation.

Model-Based Test Generation For Processor Design Verification ← introduces 100% 2e

The paper introduces model-based test generation for processor design verification.

Efficient Cross-Level Testing for Processor Verification: A RISC-V Case-Study ← mentions 90% 2e

The paper mentions model-based test generation as a related approach.

RISC-V Torture Test ← uses 90% 1e

RISC-V Torture Test is a model-based test generation approach.

Efficient Cross-Level Processor Verification using Coverage-guided Fuzzing ← compares with 75% 1e

The paper discusses model-based test generation as a related approach.

constraint-based test generation uses → 85% 1e

Model-based test generation relies on constraint-based specification to guide test generation.

RISC-V Torture Test ← implements 90% 1e

RISC-V Torture Test is a model-based test generation approach using randomized instruction sequence templates.

test generator ← uses 85% 1e

Model-based test generation is described as a technique used by test generators.

MicroTESK ← implements 90% 1e

MicroTESK is a specification-based tool for constructing test program generators, implementing model-based test generation.

CSP/SMT Solver uses → 90% 1e

Model-based test generators use CSP/SMT solvers for constraint processing.

Bayesian Network Test Generation ← part of 80% 1e

Bayesian network test generation is a specific model-based test generation approach.

LINKED ENTITIES

1 links

Model-Based Test Generation For Processor Design Verification INTRODUCES Extracted graph relationship

CITATIONS

11 sources

11 citations — click to expand

[1] Model-based test generation relies on a constraint-based specification to guide the test generation process, in contrast with classical randomized instruction-stream generation. Processor Verification using Symbolic Execution: A RISC-V Case Study

[2] Further optimizations for model-based generation propagate constraints among multiple instructions in a more effective way, as in the abstract-CSP-based instruction-stream generator. Processor Verification using Symbolic Execution: A RISC-V Case Study

[3] Model-based approaches require significant effort to provide a respective input-format specification. Processor Verification using Symbolic Execution: A RISC-V Case Study

[4] Modern coverage-guided fuzzers work by mutating randomly created data and are guided by coverage, hence they do not require an input model specification. Processor Verification using Symbolic Execution: A RISC-V Case Study

[5] An effective coverage-guided fuzzing-based processor verification methodology can be obtained by using an ISS as a reference model for the RTL processor under test. Processor Verification using Symbolic Execution: A RISC-V Case Study

[6] The cited DATE paper proposes a symbolic-execution-based processor verification approach for the RISC-V MicroRV32 processor using co-simulation between an RTL processor (translated via Verilator) and a C++ ISS, with the KLEE symbolic execution engine driving symbolic exploration. Processor Verification using Symbolic Execution: A RISC-V Case Study

[7] The cited Springer chapter lists historical processor-verification generators and references including Aharon et al. (1991) on the IBM RISC System/6000, Aharon et al. (1995) on PowerPC test program generation at IBM, the 1992 HP 9000 PA-RISC verification paper, AVPGEN (1995), and the Lichtenstein, Malka, Aharon (1994) IAAI paper on model-based test generation for processor design verification. A methodology for processor implementation verification

[8] Applying symbolic-execution tools from the SW domain to generate test vectors for RTL designs has been evaluated on specific units such as a floating-point unit, and combining static analysis with symbolic execution on execution traces of the RTL design has been proposed to systematically drive up branch coverage. Processor Verification using Symbolic Execution: A RISC-V Case Study

[9] Coverage-directed generation using symbolic techniques is cited as a related direction that combines coverage feedback with symbolic techniques for test generation. A methodology for processor implementation verification

[10] A language expert builds test models using a Java-based framework with simple but powerful modeling elements, and the toolset forms a domain-specific modeling language that domain experts use to constrain and guide generation, generate large test sets, target constrained parts of a model, or manually define specific test cases on top of the model. Using Built-In Domain-Specific Modeling Support to Guide Model-Based Test Generation

[11] FRAGGEN uses page-fragment-based state abstraction to infer better web-app models and generate regression test suites and oracles, outperforming whole-page techniques on near-duplicate detection, model precision/recall, and oracle robustness. Fragment-Based Test Generation For Web Apps