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RISC-V Torture Test

Tool

RISC-V Torture Test is a Scala-based, model-based test generation framework for RISC-V verification. It generates tests from randomized instruction-sequence templates and supports several RISC-V ISA extensions, but the cited evidence reports limitations in coverage because it relies on predefined instruction-sequence building blocks and does not support illegal instructions or exceptions.

First seen 5/25/2026
Last seen 5/30/2026
Evidence 1 chunks
Wiki v1

WIKI

Overview

RISC-V Torture Test is described in the cited verification literature as a model-based test generation approach for RISC-V processors. It is a Scala-based framework that generates tests using randomized instruction sequence templates and supports several RISC-V ISA extensions. [model-based generation; implementation and supported ISA extensions]

Test generation approach

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NEIGHBORHOOD

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RELATIONSHIPS

3 connections
Efficient Cross-Level Testing for Processor Verification: A RISC-V Case-Study ← compares with 85% 2e
The paper discusses RISC-V Torture Test as a related model-based approach and contrasts its limitations.
Model-Based Test Generation implements → 90% 1e
RISC-V Torture Test is a model-based test generation approach using randomized instruction sequence templates.
Model-Based Test Generation uses → 90% 1e
RISC-V Torture Test is a model-based test generation approach.

LINKED ENTITIES

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Model-Based Test Generation IMPLEMENTS Extracted graph relationship

CITATIONS

4 sources
4 citations — click to collapse
[1] model-based generation
[2] implementation and supported ISA extensions
[3] randomized instruction templates
[4] predefined building blocks and limitations