Overview

RISC-V Torture Test is described in the cited verification literature as a model-based test generation approach for RISC-V processors. It is a Scala-based framework that generates tests using randomized instruction sequence templates and supports several RISC-V ISA extensions. [model-based generation; implementation and supported ISA extensions]

Test generation approach

The framework generates RISC-V tests from randomized templates of instruction sequences. In the taxonomy used by the cited paper, this places RISC-V Torture Test among model-based test generation methods rather than coverage-guided fuzzing or constrained-random SystemVerilog/UVM approaches. [model-based generation; randomized instruction templates]

Reported limitations

The cited source reports that RISC-V Torture Test relies on predefined building blocks for instruction sequences. According to that source, this limits coverage. The same source also states that the approach does not support illegal instructions or exceptions. [predefined building blocks and limitations]

Relationship to model-based test generation

RISC-V Torture Test implements a model-based test generation technique for producing RISC-V test programs. [model-based generation]