Overview

“Closing the RISC-V compliance gap: Looking from the negative testing side” is a paper listed in the references of Efficient Cross-Level Testing for Processor Verification: A RISC-V Case-Study. The reference entry identifies the authors as V. Herdt, D. Große, and R. Drechsler, and states that the paper appeared in DAC, 2020.

The title indicates that the paper addresses the RISC-V compliance gap from the perspective of negative testing. The available evidence does not include the paper’s abstract, method details, evaluation, or conclusions, so those aspects cannot be summarized here without additional sources.

Bibliographic context

In the cited reference list, the paper appears near other RISC-V verification and compliance resources, including RISC-V ISA tests, the RISC-V compliance task group, RISC-V torture, RISCV-DV, riscv-formal, and formal RISC-V ISA models. This places the paper within a documented bibliography of RISC-V processor verification and compliance-related work, but the evidence only directly supports the bibliographic facts and the title-level topic.