RISC-V Vector Extension
ConceptThe RISC-V Vector Extension (RVV) is a RISC-V ISA extension for vector/SIMD-style computation. Evidence highlights RVV 1.0 support in virtual platforms, QEMU implementation details around vector state dirtiness, vector CSR state such as vstart, and current software work on NEON-to-RVV migration and AI workload tuning.
First seen 6/1/2026
Last seen 9/5/2026
Evidence 31 chunks
Wiki v1
WIKI
Overview
The RISC-V Vector Extension is a vector extension for the RISC-V architecture. It is commonly abbreviated RVV and appears in both software-porting and workload-optimization contexts, including migration of ARM NEON intrinsic code to RVV intrinsics and tensor-program optimization for RISC-V vector units. Public research describes RVV as relevant for performance-oriented SIMD migration and for acceleration of AI workloads on RISC-V CPUs. [1][2]
Programming and optimization context
NEIGHBORHOOD
8 nodes · 20 edgesgraph · RISC-V Vector extension · depth=1
RELATIONSHIPS
22 connectionsRISCover evaluates the RISC-V vector extension and finds bugs including halting instructions.
The RISC-V Vector Extension is part of the RISC-V ISA.
GhostWrite is a vulnerability in the RISC-V Vector Extension implementation on C910.
The C910 implements a pre-ratified draft version 0.7.1 of the RISC-V vector extension.
The vse128.v instruction is part of the RISC-V Vector Extension.
Vector register grouping is part of the RVV specification
Ara is the first fully open-source processor compliant with RVV 1.0 specification.
RVVTS is specifically designed to test and evaluate RVV implementations
QEMU implements the RISC-V Vector Extension as part of its RISC-V target support.
RISCV-DV generates tests targeting the RISC-V Vector extension.
Spike implements the RISC-V Vector Extension 1.0
The saturation flag (vcsr.vxsat) is part of the RVV specification
RVV Specification v1.0 is the versioned specification of the RISC-V Vector Extension.
RVV Specification v0.9 is an earlier version of the RISC-V Vector Extension specification.
Sail-RISC-V implements the RISC-V Vector Extension 1.0
Spike was adapted to support the RISC-V Vector extension version 0.7.1 specification.
RISC-V VP++ supports the RISC-V Vector Extension.
trans_rvv.c.inc implements the RISC-V Vector Extension translation logic in QEMU.
mstatus.VS is the vector state status field defined in the RISC-V Vector Extension specification.
Vector CSR state is part of the RISC-V Vector Extension.
The translation-time vector context status concept is used in QEMU to implement RISC-V Vector Extension behavior.
The RISC-V Vector Extension is an extension of the RISC-V ISA.
LINKED ENTITIES
6 linkstrans_rvv.c.inc IMPLEMENTS Extracted graph relationship
mstatus.VS PART_OF Extracted graph relationship
vector CSR state PART_OF Extracted graph relationship
translation-time vector context status PART_OF Extracted graph relationship
RISC-V PART_OF Extracted graph relationship
QEMU IMPLEMENTS Extracted graph relationship
CITATIONS
5 sources5 citations — click to expand
[1] SIMDe-based NEON-to-RVV migration work treats RVV as vector-length agnostic and reported 1.51x to 5.13x speedups on Google XNNPACK versus original SIMDe without customized RVV conversions. SIMD Everywhere Optimization from ARM NEON to RISC-V Vector Extensions
[2] TVM MetaSchedule integration for RVV targets RISC-V vector units for AI workloads and reported mean latency improvements of 46% over GCC autovectorization, 29% over muRISCV-NN, and 35% over LLVM mappings on a commercial RVV 1.0 SoC. Tensor Program Optimization for the RISC-V Vector Extension Using Probabilistic Programs
[3] The Vector specification rule quoted in the QEMU patch says vector-state-changing instructions, including vector CSR changes, move mstatus.VS from Initial or Clean to Dirty; QEMU changed RVV load/store translation helpers to always call mark_vs_dirty because stores can reset vstart. [PATCH 1/3] trans_rvv.c.inc: write CSRs must call mark_vs_dirty() too
[4] RISC-V VP++ is described as an open-source SystemC-based RISC-V virtual prototype supporting RVV version 1.0. Bringing CHERI Capabilities to Life in a Virtual Platform: CHERI-RISC-V VP++
[5] RISCover reported Vector-related findings including denial-of-service cases, ISA incompatibilities involving Vector and Base ISA, and QEMU segfaults involving Vector and cache operations. RISCover: Automatic Discovery of User-exploitable Architectural Security Vulnerabilities in Closed-Source RISC-V CPUs