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CHERI-RISC-V VP++

Tool
First seen 6/11/2026
Last seen 6/21/2026
Evidence 17 chunks

NEIGHBORHOOD

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RELATIONSHIPS

25 connections
CheriBSD evaluates → 100% 4e
CheriBSD was booted and benchmarked on CHERI-RISC-V VP++.
SystemC uses → 100% 3e
CHERI-RISC-V VP++ is built on SystemC/TLM.
Instruction Set Simulator implements → 95% 3e
CHERI-RISC-V VP++ includes an ISS for executing instructions.
RISC-V VP extends → 100% 3e
CHERI-RISC-V VP++ is an extension of the existing RISC-V VP++ virtual prototype.
virtual memory management implements → 95% 3e
CHERI-RISC-V VP++ includes virtual memory management support.
TestRIG uses → 100% 2e
CHERI-RISC-V VP++ was verified using the TestRIG framework.
Random Testing uses → 100% 2e
CHERI-RISC-V VP++ is verified using random testing.
capability implements → 100% 2e
CHERI-RISC-V VP++ implements CHERI capabilities.
Institute for Complex Systems, Johannes Kepler University Linz authored by → 95% 2e
CHERI-RISC-V VP++ was developed at the Institute for Complex Systems, Johannes Kepler University Linz.
CHERI implements → 100% 2e
CHERI-RISC-V VP++ implements CHERI architectural features in a virtual prototype.
Virtual Prototype implements → 100% 2e
CHERI-RISC-V VP++ is a virtual prototype platform.
Transaction Level Modeling uses → 100% 2e
CHERI-RISC-V VP++ is modeled at the transaction level.
bare-metal software uses → 90% 2e
CHERI-RISC-V VP++ runs bare-metal CHERI-enabled software for demonstration.
A RISC-V CHERI VP: Enabling System-Level Evaluation of the Capability-Based CHERI Architecture ← introduces 100% 2e
The paper introduces the CHERI-RISC-V VP++ as its main contribution.
CHERI-RISC-V implements → 100% 2e
CHERI-RISC-V VP++ implements the CHERI-RISC-V architecture.
CHERI-RISC-V evaluates → 100% 2e
CHERI-RISC-V VP++ enables system-level evaluation of the CHERI-RISC-V architecture.
instruction overhead evaluates → 100% 2e
CHERI-RISC-V VP++ was used to measure instruction overhead for CHERI-enabled workloads.
benchmark workload evaluates → 100% 2e
CHERI-RISC-V VP++ was used to run 10 benchmark workloads on CheriBSD.
fine-grained memory protection evaluates → 90% 1e
CHERI-RISC-V VP++ provides a platform for evaluating fine-grained memory protection via CHERI.
Andreas Hinterdorfer authored by → 100% 1e
CHERI-RISC-V VP++ was authored by Andreas Hinterdorfer as part of his master's thesis.
tagged memory implements → 90% 1e
CHERI-RISC-V VP++ implements tagged memory for capability validity tracking.
capability compression implements → 90% 1e
CHERI-RISC-V VP++ implements capability compression as part of CHERI.
RVFI-DII uses → 95% 1e
CHERI-RISC-V VP++ adds RVFI-DII support for TestRIG verification.
memory management unit implements → 95% 1e
CHERI-RISC-V VP++ includes an MMU for virtual address translation.
design space exploration evaluates → 95% 1e
CHERI-RISC-V VP++ offers a platform for early design space exploration.