CHERI-RISC-V VP++

Tool

First seen 6/11/2026

Last seen 6/11/2026

Evidence 13 chunks

NEIGHBORHOOD

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RELATIONSHIPS

20 connections

bare-metal software uses → 90% 2e

CHERI-RISC-V VP++ runs bare-metal CHERI-enabled software for demonstration.

Institute for Complex Systems, Johannes Kepler University Linz authored by → 95% 2e

CHERI-RISC-V VP++ was developed at the Institute for Complex Systems, Johannes Kepler University Linz.

RISC-V VP extends → 100% 2e

CHERI-RISC-V VP++ is a CHERI-enabled extension of the open-source RISC-V VP++ project.

CHERI implements → 100% 2e

CHERI-RISC-V VP++ implements CHERI architectural features in a virtual prototype.

Virtual Prototype implements → 100% 2e

CHERI-RISC-V VP++ is a virtual prototype platform.

TestRIG uses → 100% 2e

CHERI-RISC-V VP++ was verified using the TestRIG framework.

Random Testing uses → 100% 2e

CHERI-RISC-V VP++ is verified using random testing.

capability implements → 100% 2e

CHERI-RISC-V VP++ implements CHERI capabilities.

CheriBSD evaluates → 100% 2e

CHERI-RISC-V VP++ runs and evaluates CheriBSD.

Instruction Set Simulator implements → 95% 2e

CHERI-RISC-V VP++ includes an Instruction Set Simulator as its core CPU model.

memory management unit implements → 95% 1e

CHERI-RISC-V VP++ includes an MMU for virtual address translation.

RVFI-DII uses → 95% 1e

CHERI-RISC-V VP++ adds RVFI-DII support for TestRIG verification.

Andreas Hinterdorfer authored by → 100% 1e

CHERI-RISC-V VP++ was authored by Andreas Hinterdorfer as part of his master's thesis.

tagged memory implements → 90% 1e

CHERI-RISC-V VP++ implements tagged memory for capability validity tracking.

capability compression implements → 90% 1e

CHERI-RISC-V VP++ implements capability compression as part of CHERI.

SystemC uses → 95% 1e

CHERI-RISC-V VP++ uses SystemC for hardware modeling.

Transaction Level Modeling uses → 95% 1e

CHERI-RISC-V VP++ uses Transaction Level Modeling for communication abstraction.

virtual memory management implements → 90% 1e

CHERI-RISC-V VP++ implements virtual memory management via MMU.

fine-grained memory protection evaluates → 90% 1e

CHERI-RISC-V VP++ provides a platform for evaluating fine-grained memory protection via CHERI.

design space exploration evaluates → 95% 1e

CHERI-RISC-V VP++ offers a platform for early design space exploration.