Bare-Metal Software

Concept

Bare-metal software refers to programs that run directly on a processor or virtual prototype (VP) without an underlying operating system. In the context of the CHERI-RISC-V VP++ thesis, bare-metal software is used as a stepping stone to demonstrate and evaluate CHERI's fine-grained, capability-based memory protection on a virtual platform, progressing from simple CHERI-enabled RISC-V assembly programs to CHERI-enabled C applications.

First seen 6/11/2026

Last seen 6/11/2026

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Bare-Metal Software

Definition

In the context of the CHERI-RISC-V VP++ master's thesis, bare-metal software refers to programs executed directly on a target platform — here, the CHERI-enabled RISC-V Virtual Prototype — without an operating system mediating accesses. Such programs interact with hardware (or the VP) primitives directly, including memory-mapped I/O for peripherals and explicit stack and capability table initialization.

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CHERI-RISC-V VP++ ← uses 90% 2e

CHERI-RISC-V VP++ runs bare-metal CHERI-enabled software for demonstration.

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CITATIONS

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[1] Chapter 5 of the CHERI-RISC-V VP++ thesis is titled 'Running Bare-Metal Software on CHERI-RISC-V VP++' and explores CHERI-enabled software running directly on the virtual prototype without an operating system. CHERI-RISC-V VP++: A Virtual Prototyping Platform Enabling Fine-Grained Memory Protection

[2] Bare-metal programs on CHERI-RISC-V VP++ begin as a simple assembly program and are gradually extended in complexity to expose low-level CHERI programming details. CHERI-RISC-V VP++: A Virtual Prototyping Platform Enabling Fine-Grained Memory Protection

[3] Section 5.1 covers CHERI-enabled RISC-V assembly programs, including the initial implementation, modifications for CHERI, stack pointer initialization, and the global capability table. CHERI-RISC-V VP++: A Virtual Prototyping Platform Enabling Fine-Grained Memory Protection

[4] Section 5.2 covers CHERI-enabled C programs, including toolchain prerequisites, evaluation of boundary protection, and evaluation of function pointers, with peripheral access techniques like memory-mapped I/O adapted for CHERI's capability-based memory protection. CHERI-RISC-V VP++: A Virtual Prototyping Platform Enabling Fine-Grained Memory Protection

[5] Bare-metal software serves as a bridge between the verified CHERI implementation (Chapter 4, using TestRIG) and the booting of a full capability-enabled operating system, CheriBSD, in Chapter 6. CHERI-RISC-V VP++: A Virtual Prototyping Platform Enabling Fine-Grained Memory Protection

[6] Bare-metal programs are used to demonstrate how CHERI prevents common memory corruption bugs, confirming the correct implementation of the CHERI-RISC-V VP++. CHERI-RISC-V VP++: A Virtual Prototyping Platform Enabling Fine-Grained Memory Protection

[7] The CHERI-RISC-V VP++ master's thesis is authored by Andreas Hinterdorfer, BSc, supervised by Univ.-Prof. Dr. Daniel Große and DI Manfred Schlägl, at the Institute for Complex Systems, Johannes Kepler University Linz, submitted September 2025. CHERI-RISC-V VP++: A Virtual Prototyping Platform Enabling Fine-Grained Memory Protection