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STIMSMITH

Instruction Set Simulator (ISS)

Tool WIKI v2 · 5/30/2026

In the provided cross-level processor verification flow, an Instruction Set Simulator (ISS) is used as the reference model in tight co-simulation with an RTL core. Coverage is measured from the ISS execution state, while a comparator checks ISS and RTL register-value changes to detect functional differences.

Overview

In the evidenced cross-level processor verification approach, the Instruction Set Simulator (ISS) is used as a reference model alongside an RTL core. The setup integrates the ISS and RTL core in an efficient co-simulation compiled into a single binary with in-memory communication. The approach generates endless instruction streams and uses the ISS reference execution as part of the verification loop. [C1]

Role in coverage-guided co-simulation

The flow uses randomized, coverage-guided instruction stream generation. Coverage information is continuously updated from the execution state of the ISS, and the paper describes using Coverage-guided Aging to smooth the coverage distribution of the randomized instruction stream over time. [C2]

After instructions execute, the RTL core and ISS write their results to separated memories. The Coverage-Observer then measures functional coverage based on the ISS execution state, performs coverage aging, and provides hints to the Instruction-Injector when functionality should be covered again. [C3]

Comparison against the RTL core

The Comparator is responsible for finding functional differences between the RTL core and the ISS. It compares register values from both sides. Because the RTL core and ISS do not have identical timing behavior, the Comparator logs value changes and compares changes at the same position. If it finds a difference, it exits the simulation. [C4]

Handling RTL fetch behavior

The flow accounts for RTL microarchitectural effects such as pipelining, prefetching, and fetch buffering. A Core Adapter checks for addresses that were not fetched by the ISS, fills them with randomized values that were not generated by InstrGen, and forwards them to the RTL core. [C5]

Evaluation configuration

In the reported evaluation, the device under test was a 32-bit pipelined RISC-V core from the MINRES The Good Core series. The reference model was the ISS from the open-source SystemC-based RISC-V VP. The RTL core was translated to C++ using Verilator and integrated with the ISS in a SystemC test bench. For the evaluation, both the core and ISS were configured to support the RISC-V subset RV32IMCZicsrZifencei. [C6]

The experiments used a SystemC simulation time limit of 1 second, corresponding to approximately 20 million instructions in the reported setup. [C7]

LINKED ENTITIES

5 links
Cross-level processor verification via endless randomized instruction stream generation with coverage-guided aging USES
Google RISC-V Design Verification (DV) Framework USES
Coverage-Observer USES
Comparator USES
Core-Adapter USES

CITATIONS

7 sources
7 citations
[1] The ISS is used as a reference model in a tight co-simulation with an RTL core, compiled into a single binary with in-memory communication. Cross-Level Processor Verification via
[2] Coverage information is continuously updated based on the execution state of the ISS and used with Coverage-guided Aging. Cross-Level Processor Verification via
[3] After execution, the RTL core and ISS write results to separated memories; the Coverage-Observer measures functional coverage from the ISS execution state, performs coverage aging, and gives hints to the Instruction-Injector. Cross-Level Processor Verification via
[4] The Comparator compares ISS and RTL register values, logs value changes to account for timing differences, and exits the simulation when it finds differences. Cross-Level Processor Verification via
[5] The Core Adapter handles RTL fetch effects by checking addresses not fetched by the ISS, filling them with randomized values not generated by InstrGen, and forwarding them to the RTL core. Cross-Level Processor Verification via
[6] The evaluation used a 32-bit pipelined RISC-V TGC core as DUT, the ISS from the open-source SystemC-based RISC-V VP as reference, Verilator for RTL-to-C++ translation, and a SystemC test bench; both core and ISS supported RV32IMCZicsrZifencei. Cross-Level Processor Verification via
[7] The reported experiments used a 1-second SystemC simulation time limit, approximately 20 million instructions. Cross-Level Processor Verification via

VERSION HISTORY

v2 · 5/30/2026 · gpt-5.5 (current)
v1 · 5/26/2026 · gpt-5.5