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Core Adapter

Tool

Core Adapter is a co-simulation support tool described in cross-level processor verification. It bridges fetch-behavior differences between an Instruction Set Simulator (ISS) and an RTL processor core by detecting instruction addresses not fetched by the ISS, filling those locations with randomized values, and forwarding them to the RTL core.

First seen 5/29/2026
Last seen 6/2/2026
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Overview

Core Adapter is a tool component used in cross-level processor verification to account for RTL-core micro-architectural behavior that is not directly mirrored by an Instruction Set Simulator (ISS). In the cited verification setup, the RTL core may exhibit behaviors such as pipelining, pre-fetching, and fetch-buffering, so a Core Adapter is inserted to handle instruction addresses that the RTL core requests but the ISS did not fetch.

Role in cross-level verification

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NEIGHBORHOOD

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RELATIONSHIPS

3 connections
Cross-level processor verification via endless randomized instruction stream generation with coverage-guided aging ← uses 100% 4e
The paper uses Core-Adapter to handle micro-architectural differences between ISS and RTL core.
Instruction Set Simulator (ISS) uses → 90% 2e
Core-Adapter checks for addresses not fetched by ISS and fills them
Pipelined Processor Verification implements → 85% 1e
Core Adapter handles pipeline-specific micro-architectural details.

LINKED ENTITIES

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Cross-level processor verification via endless randomized instruction stream generation with coverage-guided aging USES Extracted graph relationship
Instruction Set Simulator (ISS) USES Extracted graph relationship
Pipelined Processor Verification IMPLEMENTS Extracted graph relationship

CITATIONS

3 sources
3 citations — click to collapse
[1] The Core Adapter is used to account for RTL micro-architectural details such as pipelining, pre-fetching, and fetch-buffering. Cross-Level Processor Verification via
[2] The Core Adapter checks addresses not fetched by the ISS, fills them with randomized values not generated by InstrGen, and forwards them to the RTL core. Cross-Level Processor Verification via
[3] In the described flow, after instruction execution, the core and ISS write results to separated memories. Cross-Level Processor Verification via