Overview

Core Adapter is a tool component used in cross-level processor verification to account for RTL-core micro-architectural behavior that is not directly mirrored by an Instruction Set Simulator (ISS). In the cited verification setup, the RTL core may exhibit behaviors such as pipelining, pre-fetching, and fetch-buffering, so a Core Adapter is inserted to handle instruction addresses that the RTL core requests but the ISS did not fetch.

Role in cross-level verification

The Core Adapter checks for addresses that were not fetched by the ISS. When such addresses are encountered, it fills them with randomized values that were not generated by the instruction generator, and then forwards them to the RTL core. This allows the RTL core to continue receiving instruction data even when its fetch behavior diverges from the ISS due to micro-architectural effects.

Verification context

In the referenced cross-level verification flow, the RTL core and the ISS execute and write their results to separate memories. Other components in the same flow include a Coverage-Observer, an Instruction-Injector, and a Comparator. The Core Adapter specifically addresses the mismatch in fetch behavior caused by RTL-level details, while later comparison logic is responsible for detecting functional differences between the RTL core and ISS.