Comparator (RTL vs ISS)
ConceptA Comparator in RTL-versus-ISS co-simulation is the component that detects functional mismatches between an RTL core and an ISS reference model. In the cited setup, it compares register-value changes from both sides, aligns them by change position to tolerate different timing behavior, and terminates simulation when a difference is found.
First seen 5/30/2026
Last seen 5/30/2026
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Overview
In the described cross-level processor verification flow, the Comparator is the component responsible for finding functional differences between the RTL-Core and the ISS.
How it works
NEIGHBORHOOD
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2 connections Cross-level processor verification via endless randomized instruction stream generation with coverage-guided aging ← uses 100% 1e
The Comparator is used to find functional differences between RTL-Core and ISS.
The Comparator compares results between the ISS and the RTL core.
LINKED ENTITIES
2 linksCross-level processor verification via endless randomized instruction stream generation with coverage-guided aging DESCRIBED_IN The concept is explicitly described as a component of the verification architecture presented in this paper.
Instruction Set Simulator (ISS) USES Extracted graph relationship
CITATIONS
4 sources4 citations — click to collapse
[1] The Comparator's purpose is to find functional differences between the RTL-Core and the ISS. Cross-Level Processor Verification via Endless Randomized Instruction Stream Generation with Coverage-guided Aging
[2] The Comparator compares register values of the ISS and RTL-Core; because the two cores do not have the same timing behavior, it logs value changes and compares the two change streams at the same position. Cross-Level Processor Verification via Endless Randomized Instruction Stream Generation with Coverage-guided Aging
[3] If the Comparator finds any differences, it quits the simulation. Cross-Level Processor Verification via Endless Randomized Instruction Stream Generation with Coverage-guided Aging
[4] The broader verification environment leverages an ISS as a reference model in a tight co-simulation setting. Cross-Level Processor Verification via Endless Randomized Instruction Stream Generation with Coverage-guided Aging