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STIMSMITH

Comparator (RTL vs ISS)

Concept WIKI v1 · 5/30/2026

A Comparator in RTL-versus-ISS co-simulation is the component that detects functional mismatches between an RTL core and an ISS reference model. In the cited setup, it compares register-value changes from both sides, aligns them by change position to tolerate different timing behavior, and terminates simulation when a difference is found.

Overview

In the described cross-level processor verification flow, the Comparator is the component responsible for finding functional differences between the RTL-Core and the ISS.

How it works

The Comparator operates on register values produced by the two execution domains. A direct time-aligned comparison is not sufficient, because the RTL core and the ISS do not have the same timing behavior. To handle this, the Comparator:

  • logs register-value changes from the RTL core and the ISS,
  • continuously compares the logged changes at the same position, and
  • reports a mismatch as soon as a difference is observed.

Behavior on mismatch

If the Comparator detects any difference between the RTL core and the ISS, the simulation is stopped.

Context in the verification setup

The Comparator is part of a broader cross-level processor verification environment that uses an ISS as a reference model. In that setup, the Comparator works alongside other components such as the core adapter, coverage observer, and instruction injector.

LINKED ENTITIES

2 links
Cross-level processor verification via endless randomized instruction stream generation with coverage-guided aging DESCRIBED_IN
Instruction Set Simulator (ISS) USES

CITATIONS

4 sources
4 citations
[1] The Comparator's purpose is to find functional differences between the RTL-Core and the ISS. Cross-Level Processor Verification via Endless Randomized Instruction Stream Generation with Coverage-guided Aging
[2] The Comparator compares register values of the ISS and RTL-Core; because the two cores do not have the same timing behavior, it logs value changes and compares the two change streams at the same position. Cross-Level Processor Verification via Endless Randomized Instruction Stream Generation with Coverage-guided Aging
[3] If the Comparator finds any differences, it quits the simulation. Cross-Level Processor Verification via Endless Randomized Instruction Stream Generation with Coverage-guided Aging
[4] The broader verification environment leverages an ISS as a reference model in a tight co-simulation setting. Cross-Level Processor Verification via Endless Randomized Instruction Stream Generation with Coverage-guided Aging