Within the provided technical evidence, Google is represented by its association with RISC-V DV / the open-source RISC-V Design Verification framework, a constrained-random RISC-V instruction-stream generation and co-simulation framework used for processor verification.
First seen 5/25/2026
Last seen 7/20/2026
Evidence 39 chunks
Wiki v5
WIKI
The supplied evidence supports a narrow technical profile of Google: it identifies Google as the organization associated with RISC-V DV, also described as Google’s open-source RISC-V Design Verification (DV) framework. The evidence does not support broader claims about Google’s corporate history, product portfolio, infrastructure, cloud services, search systems, or AI systems. [C1]
RISC-V DV / RISC-V Design Verification framework
NEIGHBORHOOD
3 nodes · 3 edgesgraph · Google · depth=1
RELATIONSHIPS
17 connectionsRISCV-DV is an open-source project created by Google.
RISCV-DV is described as Google's constrained-random generator.
Google developed and open-sourced RISCV-DV
Google's open-source RISC-V DV framework is referenced.
RISCV-DV was originally developed by Google.
The RISC-V Random Instruction Generator is attributed to Google.
The RISCV Random Instruction Generator is attributed to Google.
OpenTitan is Google's open-source chip project.
AFL was developed at Google.
Google developed the riscv-dv instruction stream generator (also known as COREV-DV).
All authors are affiliated with Google, indicating the paper was published by Google.
Google developed the open-source RISC-V DV framework.
OSS-Fuzz is a product of Google.
The RISC-V DV framework is an open-source framework published by Google.
OpenTitan is co-developed by Google.
The RISC-V DV framework is Google's open-source tool.
Google developed and introduced the RISC-V Random Instruction Generator tool.
LINKED ENTITIES
1 linksCITATIONS
5 sources5 citations — click to expand
[1] Google is associated with RISC-V DV / the open-source RISC-V Design Verification framework, and broader Google claims are not supported by the supplied evidence. Cross-Level Processor Verification via
[2] RISC-V DV is described as a Google test-generation approach using SystemVerilog and UVM to generate constrained-random RISC-V instruction streams, with log-file-based co-simulation comparison and support for RISC-V extensions and CSR testing. Efficient Cross-Level Testing for
[3] Google's open-source RISC-V Design Verification framework uses ISS/RTL co-simulation, SystemVerilog constraint-based specifications, one-at-a-time RISC-V assembly test generation, configurable instruction-set specifications, and execution-log comparison. Cross-Level Processor Verification via
[4] The 2020 paper reports that RISC-V DV restricts generated instruction streams to avoid infinite loops and platform-dependent memory-access operations and has significant performance overhead due to its generic simulator/RTL-core support goals. Efficient Cross-Level Testing for
[5] The 2022 paper reports RISC-V DV limitations including restricted tests, short one-by-one instruction sequences with processor reset between tests, filesystem-related co-simulation overhead, and lack of dynamic coverage guidance. Cross-Level Processor Verification via