The supplied evidence supports a narrow technical profile of Google: it identifies Google as the organization associated with RISC-V DV, also described as Google’s open-source RISC-V Design Verification (DV) framework. The evidence does not support broader claims about Google’s corporate history, product portfolio, infrastructure, cloud services, search systems, or AI systems. [C1]
RISC-V DV / RISC-V Design Verification framework
A 2020 processor-verification paper describes RISC-V DV as a test-generation approach “by Google.” In that account, RISC-V DV uses SystemVerilog together with UVM to continuously generate RISC-V instruction streams from constrained-random descriptions. Each generated instruction stream is treated as a test case, and the framework provides a high-level co-simulation interface for comparing results between simulators using execution log files. The paper also reports support for several RISC-V instruction-set extensions and CSR-testing capabilities. [C2]
A 2022 cross-level processor-verification paper describes Google’s open-source RISC-V Design Verification (DV) framework as a co-simulation-based approach that uses an Instruction Set Simulator (ISS) as a functional reference model for an RTL processor under test. The framework applies constraint-based specification techniques in SystemVerilog to generate RISC-V assembly tests one after another. Different RISC-V instruction sets are supported by selecting and combining the corresponding constraint-based specifications, and execution results from the ISS and RTL processor core are compared through execution log files. [C3]
Reported limitations in verification use
The cited papers also identify limitations of RISC-V DV in the contexts they discuss. The 2020 paper states that generated instruction streams are restricted to avoid infinite loops and platform-dependent memory-access operations, and that the framework has significant performance overhead because it is generic and designed to support a broad range of simulators and RTL cores. [C4]
The 2022 paper gives a more detailed characterization of those limitations: to keep the framework generic, generated tests use a restricted instruction set; tests are generated one by one, so only comparatively short instruction sequences are considered and the processor-under-test state is regularly reset for each new test execution; co-simulation has filesystem-related overhead because each RISC-V assembly test must be compiled, loaded into the simulator, and produce a log file for comparison; and the generator is not designed to be dynamically guided by coverage information obtained during test execution. [C5]
Scope note
No claims beyond Google’s evidenced association with RISC-V DV / the RISC-V Design Verification framework are made here, because no supporting evidence was provided for other Google technologies or organizational details.