Overview

Google RISC-V Design Verification (DV) Framework is described in the DATE 2022 paper Cross-Level Processor Verification via Endless Randomized Instruction Stream Generation with Coverage-guided Aging as an open-source RISC-V processor verification framework. The paper places it in the class of simulation-based RTL processor verification methods that use co-simulation with an Instruction Set Simulator (ISS) as a functional reference model for the RTL processor under test.

Test generation model

The framework applies constraint-based specification techniques in SystemVerilog to generate RISC-V assembly tests one after another. Different RISC-V instruction sets are supported by selecting and combining the relevant constraint-based specifications.

Co-simulation and checking

In the verification flow described by the paper, an ISS is used as the reference model for the RTL processor. Execution results from the ISS and the RTL processor core are compared through execution log files.

Reported limitations

The DATE 2022 paper identifies several limitations of the framework in comparison with the paper's proposed endless, coverage-guided instruction stream approach:

• The generated tests use a restricted instruction set to avoid problems with infinite loops and platform-dependent memory-access operations.
• Tests are generated one by one, so the framework considers comparatively short instruction sequences and regularly resets the processor-under-test state for each new test execution.
• The co-simulation flow has performance overhead from filesystem communication, because each RISC-V assembly test must be compiled, loaded into the relevant simulator, and produce a log file for comparison.
• The test generator is not designed to be dynamically guided by coverage information obtained during test execution progress.

Relationship to cross-level endless-random testing

The cited cross-level verification paper contrasts Google RISC-V DV with an approach that generates endless instruction streams, tightly integrates the ISS and RTL core into a single compiled binary, uses in-memory communication, and updates coverage information dynamically from ISS execution state. In that comparison, Google RISC-V DV represents a powerful generic RISC-V DV baseline based on per-test generation and log-file-based ISS/RTL comparison, while the paper's proposed approach targets longer-running, coverage-guided streams and lower co-simulation overhead.