Overview

Cross-level processor verification is a processor-verification technique that compares a processor design at one abstraction level (typically a cycle-accurate RTL implementation) against a reference model at a different abstraction level (typically an instruction set simulator, ISS) inside a single, tightly coupled co-simulation. In the cited work, the ISS and the RTL core are integrated into an efficient co-simulation compiled into a single binary with in-memory communication, and a comparator checks for functional differences between the two executions. [C1]

The motivation for using a cross-level setup is that RISC-V is a modular ISA built around a mandatory base integer instruction set and a family of optional standard and custom instruction-set extensions, and the resulting configuration space, combined with micro-architectural features such as pipelining and branch prediction, makes verification challenging. [C2]

FDL 2020 predecessor work

The DATE 2022 approach conceptually builds on a prior academic study, referred to in the paper as the previous academic work [3], which established efficient cross-level testing for processor verification on a RISC-V case study at the 2020 Forum for Specification and Design Languages (FDL). [C3] The FDL 2020 study is the direct predecessor of the DATE 2022 method: it already generated endless instruction streams and integrated the ISS with the RTL core in a co-simulation compiled into a single binary with in-memory communication, but its instruction-stream generator was based on a simple randomized strategy with no runtime coverage information, which made it difficult to continuously achieve a broad and deep test coverage in endless instruction streams. [C4]

DATE 2022 coverage-guided approach

The DATE 2022 paper Cross-Level Processor Verification via Endless Randomized Instruction Stream Generation with Coverage-guided Aging proposes a cross-level verification method based on a randomized, coverage-guided instruction-stream generator. The generator produces an endless and unrestricted instruction stream that evolves dynamically at runtime based on observed coverage information, while the ISS acts as the reference model in a tight co-simulation setting. [C5]

A key design choice is that the instruction stream can be generated without restrictions: the cited setup supports arbitrary combinations of load/store instructions, Control and Status Register (CSR) instructions, and infinite loops, enabling a comprehensive randomized test approach. [C6] To prevent the stream from stagnating, the approach introduces coverage-guided aging, which smooths out the coverage distribution of the randomized instruction stream over time and helps find intricate corner-case bugs in the RTL core. [C7]

Main components

Figure 1 of the DATE 2022 paper shows the overall verification architecture, which consists of two parallel paths that are driven by the same seeds: an upper path containing an instruction generator (InstrGen) feeding a Core-Adapter, an RTL core with its own RTL memory; and a lower path containing another instruction generator feeding an ISS with its own ISS memory. The two paths are linked by an Instruction-Injector and a Coverage-Observer, and their outputs are compared by a Comparator. [C8]

Coverage information is continuously updated based on the execution state of the ISS, and the Coverage-Observer uses the novel concept of coverage-guided aging to provide hints to the Instruction-Injector when already-covered functionality should be revisited. This makes it possible to achieve a much more regular coverage distribution of the randomized instruction stream over time. [C7]

Evaluation context

The DATE 2022 evaluation used the 32-bit pipelined RISC-V core from the MINRES The Good Core (TGC) series as the device under test, and the open-source ISS of a SystemC-based RISC-V virtual platform as the reference model. The experiments demonstrated the effectiveness of the approach by achieving a more regular coverage distribution of the randomized instruction stream than prior randomized strategies. [C9]