MINRES TGF RISC-V Core

Tool

The MINRES TGF RISC-V Core is described in the supplied evidence as a 32-bit pipelined RISC-V core from the MINRES The Good Folk series that was used as an industrial case study for cross-level RTL processor verification. The reported verification setup used an endless on-the-fly instruction stream, an Instruction Set Simulator as a reference model, and a core adapter that monitored pipeline activity and exposed register values for comparison.

First seen 5/25/2026

Last seen 5/25/2026

Evidence 2 chunks

Wiki v1

WIKI

Overview

The MINRES TGF RISC-V Core is identified in the evidence as the 32-bit pipelined RISC-V core of the MINRES The Good Folk (TGF) Series. It appears as an industrial case study for a cross-level verification approach targeting RISC-V RTL processor designs. [C1]

Role in verification research

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NEIGHBORHOOD

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LINKED ENTITIES

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Cross-Level Testing VERIFIED_USING Extracted graph relationship

MINRES Technologies GmbH PRODUCED_BY Extracted graph relationship

Core Adapter MONITORS Extracted graph relationship

CITATIONS

8 sources

8 citations — click to expand

[1] C1: The entity is a 32-bit pipelined RISC-V core of the MINRES The Good Folk (TGF) Series used as an industrial verification case study.

[2] C2: The verification setup generated an endless unrestricted instruction stream, used an ISS as reference model, fed both ISS and RTL core, and compared results after each executed instruction.

[3] C3: The reported approach found several serious bugs in the industrial core and processed more than 200 million instructions per hour on a standard laptop.

[4] C4: The core adapter observes internal core signals, especially pipeline behavior, notifies the controller on instruction completion, preserves order for illegal instructions, and exposes register values for ISS comparison.

[5] C5: Pipeline details such as multi-cycle operations create delays and gaps, requiring pipeline understanding to detect completed instructions.

[6] C6: Endless unrestricted instruction generation complicates ISS/RTL synchronization because the RTL pipeline pre-fetches instructions and jumps or traps can change which fetched instructions execute.

[7] C7: The setup matches ISS fetches against pending instructions and reports a mismatch if the ISS fetches an instruction not delivered to the RTL core.

[8] C8: The instruction generator can fully randomize instructions and inject random opcodes to produce valid instructions while keeping fields randomized.