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STIMSMITH

MINRES TGF RISC-V Core

Tool WIKI v1 · 5/25/2026

The MINRES TGF RISC-V Core is described in the supplied evidence as a 32-bit pipelined RISC-V core from the MINRES The Good Folk series that was used as an industrial case study for cross-level RTL processor verification. The reported verification setup used an endless on-the-fly instruction stream, an Instruction Set Simulator as a reference model, and a core adapter that monitored pipeline activity and exposed register values for comparison.

Overview

The MINRES TGF RISC-V Core is identified in the evidence as the 32-bit pipelined RISC-V core of the MINRES The Good Folk (TGF) Series. It appears as an industrial case study for a cross-level verification approach targeting RISC-V RTL processor designs. [C1]

Role in verification research

In the cited case study, the core under test was verified using a tightly coupled cross-level co-simulation setup. The approach generated an endless instruction stream without restrictions by evolving the instruction stream on the fly during simulation. An Instruction Set Simulator (ISS) served as the reference model for the RTL core under test. The testbench fed the generated stream to both the ISS and the RTL core and compared results after each executed instruction, with the goal of detecting RTL errors immediately when they occurred. [C2]

The evidence reports that this approach was effective in finding several serious bugs in the industrial core and achieved more than 200 million processed instructions per hour on a standard laptop. [C3]

Core adapter interface

The verification setup used a core adapter to hide implementation details of the core and provide a clean testing interface. The adapter observed internal signal changes, especially pipeline-related behavior, and notified the test controller each time the RTL core completed an instruction. It also preserved the correct instruction order in the presence of illegal instructions and provided access to RTL register values so they could be compared with the ISS. [C4]

This adapter was necessary because pipeline behavior complicates instruction completion detection. The evidence notes that multi-cycle operations can introduce delays and gaps, and that a deep understanding of the pipeline is required to know when an instruction has actually completed. [C5]

Instruction stream matching challenges

The verification method aimed to generate an endless, unrestricted instruction stream, but this complicated keeping the RTL core and ISS aligned. The RTL core could pre-fetch several instructions because of its pipeline. If a jump or trap occurred, some pre-fetched instructions might not execute, causing the ISS to fetch a different sequence of program counters than the RTL core. Short jumps or traps could also cause a new RTL instruction fetch before the ISS had an opportunity to fetch the same instruction. [C6]

To address this, the setup matched ISS fetch requests against a queue of pending instructions. If a matching instruction was found, it was returned; otherwise, the setup reported a mismatch between the RTL core and ISS because the ISS attempted to fetch an instruction that had not been delivered to the RTL core. [C7]

Instruction generation

The co-simulation setup enabled endless generation of unrestricted instructions. Its baseline generation algorithm fully randomized generated instructions, and modifications could guide generation toward interesting cases. One described modification injected a random instruction opcode to create a valid instruction while keeping instruction fields randomized, increasing the chance that legal instructions were exercised. [C8]

LINKED ENTITIES

3 links
Cross-Level Testing VERIFIED_USING
MINRES Technologies GmbH PRODUCED_BY
Core Adapter MONITORS

CITATIONS

8 sources
8 citations
[1] C1: The entity is a 32-bit pipelined RISC-V core of the MINRES The Good Folk (TGF) Series used as an industrial verification case study.
[2] C2: The verification setup generated an endless unrestricted instruction stream, used an ISS as reference model, fed both ISS and RTL core, and compared results after each executed instruction.
[3] C3: The reported approach found several serious bugs in the industrial core and processed more than 200 million instructions per hour on a standard laptop.
[4] C4: The core adapter observes internal core signals, especially pipeline behavior, notifies the controller on instruction completion, preserves order for illegal instructions, and exposes register values for ISS comparison.
[5] C5: Pipeline details such as multi-cycle operations create delays and gaps, requiring pipeline understanding to detect completed instructions.
[6] C6: Endless unrestricted instruction generation complicates ISS/RTL synchronization because the RTL pipeline pre-fetches instructions and jumps or traps can change which fetched instructions execute.
[7] C7: The setup matches ISS fetches against pending instructions and reports a mismatch if the ISS fetches an instruction not delivered to the RTL core.
[8] C8: The instruction generator can fully randomize instructions and inject random opcodes to produce valid instructions while keeping fields randomized.