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Core Adapter

CodeArtifact WIKI v1 · 5/25/2026

The Core Adapter is a code artifact in a SystemC-based co-simulation testbench for processor verification. It abstracts RTL-core implementation details by observing internal core signal changes, especially pipeline activity, notifying the test controller when an instruction completes, preserving ordering for illegal instructions, and exposing RTL register values for comparison with an ISS reference model.

Overview

The Core Adapter is part of a SystemC-based co-simulation setup for processor verification. The broader testbench co-simulates an RTL core under test with an ISS reference model, while a test controller repeatedly executes one instruction on the RTL core, executes the same instruction on the ISS, and compares their execution states, especially register state. [C1]

Within that setup, the Core Adapter provides a clean testing interface over implementation-specific RTL details. It is introduced because detecting instruction completion in a pipelined RTL core can require detailed knowledge of pipeline behavior, including multi-cycle operations, delays, and gaps. [C2]

Responsibilities

The Core Adapter has three primary responsibilities:

  1. Hide core implementation details
    The adapter abstracts the internal details of the RTL core and exposes a cleaner interface for the verification testbench. [C2]

  2. Detect completed RTL instructions
    It observes internal signal changes of the core, particularly pipeline-related signals, and notifies the test controller each time the RTL core completes an instruction. [C2]

  3. Expose RTL register state
    It provides access to RTL-core register values so they can be compared against the ISS state. [C2]

The adapter also preserves the correct instruction order in cases involving illegal instructions. [C2]

Role in the co-simulation flow

The co-simulation testbench is implemented in SystemC and coordinates execution between an RTL core and an ISS reference model. The test controller lets the RTL core execute one instruction, then lets the ISS execute the same instruction, and finally compares the resulting execution states. If the states mismatch, an error is reported; otherwise, testing continues. [C1]

In this flow, the Core Adapter sits on the RTL side of the testbench. It bridges low-level RTL signal behavior and the higher-level test controller by reporting instruction completion and making RTL register data available for comparison. [C2]

Instruction-stream implications

The adapter is used in a setup where unrestricted instruction streams are generated. This is complicated by RTL prefetching: the RTL core may fetch instructions that are never executed after jumps or traps, while the ISS may fetch a different sequence of program counters. [C3]

The evidence explicitly notes that completed instructions are not directly fed from the Core Adapter to the ISS, because doing so would compromise the testing approach by relying on instruction propagation in the RTL core, which is itself under test. [C3]

Related entities

  • [[Co-Simulation Testbench]] — contains the Core Adapter as part of the processor-verification co-simulation architecture.
  • [[MINRES TGF RISC-V Core]] — related as the monitored RTL core in the provided entity relationship; the evidence supports the general role of the Core Adapter as observing internal RTL-core signal changes.

LINKED ENTITIES

2 links
Co-Simulation Testbench CONTAINS
MINRES TGF RISC-V Core MONITORS

CITATIONS

3 sources
3 citations
[1] The co-simulation testbench is implemented in SystemC and coordinates execution between an RTL core under test and an ISS reference model, with the test controller executing and comparing one instruction at a time.
[2] The Core Adapter hides RTL-core implementation details, observes internal core signal changes especially in the pipeline, notifies the test controller when the RTL core completes an instruction, preserves correct order for illegal instructions, and provides access to RTL register values.
[3] Instruction-stream matching is complicated by RTL prefetching, jumps, and traps; the completed instruction sequence is not directly fed from the Core Adapter to the ISS because that would rely on instruction propagation in the RTL core under test.