Overview

The instruction generation algorithm is the instruction-stream generator described in Efficient Cross-Level Testing for Processor Verification: A RISC-V Case-Study. It is used in a co-simulation-based testing setup whose goal is to generate an endless, unrestricted instruction stream for comparing an RTL core with an instruction set simulator (ISS). The paper identifies fully randomized instruction generation as the baseline, then adds modifications that guide generation toward more interesting and more often legal RISC-V instructions. [C1]

A key motivation is that pure randomization tends to produce illegal instructions because the illegal-instruction state space is much larger than the legal-instruction state space. The algorithm therefore begins with a random 32-bit instruction word but often injects a valid opcode and sometimes applies field-level mutation rules derived from RISC-V instruction structure. [C2]