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instruction field mutation

Technique

Instruction field mutation is a guided instruction-generation technique used in RISC-V processor verification. It modifies selected fields of a randomized instruction according to predefined, format-aware rules, such as forcing destination and source registers to match, setting the destination register to zero, injecting boundary immediates, or selecting supported CSR fields.

First seen 5/26/2026
Last seen 5/30/2026
Evidence 2 chunks
Wiki v1

WIKI

Overview

Instruction field mutation is a modification step in an instruction stream generator for RISC-V verification. The generator starts from randomized 32-bit instruction words and uses additional guidance to produce interesting cases for testing rather than relying only on pure randomization. Pure randomization is described as tending to generate illegal instructions because the state space of illegal instructions is significantly larger than that of legal instructions. [definition-and-motivation]

Role in instruction generation

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RELATIONSHIPS

3 connections
Efficient Cross-Level Testing for Processor Verification: A RISC-V Case-Study ← uses 100% 2e
The paper uses instruction field mutation to guide test generation towards interesting cases.
on-the-fly instruction stream generation ← uses 100% 1e
On-the-fly instruction stream generation uses instruction field mutation to target interesting cases.
instruction generation algorithm ← uses 100% 1e
The instruction generation algorithm applies field mutation rules.

CITATIONS

9 sources
9 citations — click to expand
[1] definition-and-motivation
[2] algorithm-placement
[3] rule-basis
[4] immediate-rules
[5] register-rules
[6] csr-rule
[7] addi-example
[8] verification-context
[9] evaluation-context