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on-the-fly instruction stream generation

Technique

On-the-fly instruction stream generation is a processor-verification technique used in a RISC-V cross-level testing approach. In the provided evidence, the technique generates an endless instruction stream during simulation, feeds newly generated instructions to the RTL core, and supplies matching instructions to a reference ISS so both models can be compared on observable architectural state.

First seen 5/26/2026
Last seen 5/30/2026
Evidence 9 chunks
Wiki v2

WIKI

Overview

On-the-fly instruction stream generation is a processor-verification technique described as part of a cross-level testing approach. The approach generates an endless instruction stream during simulation and feeds that stream to both an RTL core and an instruction-set simulator (ISS) in a co-simulation testbench. The RTL instruction fetch path always generates a new instruction, even if the same program counter (PC) has already been fetched, while the ISS receives the corresponding instruction that was fetched by the RTL core. [claim: overview_and_cosimulation]

The instruction stream sits between the instruction generator and the memory interfaces. For RTL fetches, the stream calls the instruction generator, stores the generated instruction together with the PC in a pending-instruction queue, and returns the instruction. For ISS fetches, the stream searches for the matching instruction previously fetched by the RTL core. [claim: stream_placement_and_fetch_flow]

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NEIGHBORHOOD

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RELATIONSHIPS

10 connections
Efficient Cross-Level Testing for Processor Verification: A RISC-V Case-Study ← introduces 100% 2e
The paper introduces on-the-fly instruction stream generation as part of its approach.
Cross-Level Testing ← uses 100% 2e
Cross-level testing relies on on-the-fly instruction stream generation to drive verification.
Instruction Stream Generation ← part of 90% 2e
On-the-fly instruction stream generation is a specific form of instruction stream generation done during simulation.
Efficient Cross-Level Testing for Processor Verification: A RISC-V Case-Study ← uses 100% 2e
The paper generates instructions on-the-fly during simulation.
cross-level testing ← uses 95% 2e
Cross-level testing generates instructions on-the-fly.
Instruction Stream Generation uses → 90% 2e
On-the-fly instruction stream generation implements the general concept of instruction stream generation.
opcode injection uses → 100% 1e
On-the-fly instruction stream generation uses opcode injection to create valid instructions.
instruction field mutation uses → 100% 1e
On-the-fly instruction stream generation uses instruction field mutation to target interesting cases.
instruction sequence generation uses → 100% 1e
On-the-fly instruction stream generation uses instruction sequences designed to perform specific tasks.
instruction generation algorithm ← implements 100% 1e
The instruction generation algorithm implements the on-the-fly instruction stream generation technique.

LINKED ENTITIES

3 links
Efficient Cross-Level Testing for Processor Verification: A RISC-V Case-Study USES Extracted graph relationship
cross-level testing USES Extracted graph relationship
Instruction Stream Generation USES Extracted graph relationship

CITATIONS

10 sources
10 citations — click to expand
[1] overview_and_cosimulation Efficient Cross-Level Testing for
[2] stream_placement_and_fetch_flow Efficient Cross-Level Testing for
[3] memory_interface_context Efficient Cross-Level Testing for
[4] lazy_data_memory Efficient Cross-Level Testing for
[5] unrestricted_generation Efficient Cross-Level Testing for
[6] architectural_state_comparison Efficient Cross-Level Testing for
[7] completion_detection_challenge Efficient Cross-Level Testing for
[8] pc_matching_problem Efficient Cross-Level Testing for
[9] pending_queue_solution Efficient Cross-Level Testing for
[10] matching_purpose Efficient Cross-Level Testing for