Instruction Stream Generation

Technique

Instruction Stream Generation is a processor-verification technique that produces instruction sequences for simulation or co-simulation. In the provided RISC-V verification evidence, it is used to generate endless, unrestricted instruction streams, with random generation as a baseline and optional guidance such as opcode injection to increase legal-instruction coverage.

First seen 5/25/2026

Last seen 5/26/2026

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Overview

Instruction Stream Generation is a test-generation technique for processor verification in which streams of instructions are produced and supplied to a processor model, simulator, or RTL core. In the provided RISC-V cross-level verification evidence, the stated goal is to generate an endless and unrestricted instruction stream for co-simulation, with the RTL core and instruction-set simulator (ISS) expected to behave identically in their observable architectural state, especially register updates. [c1]

Role in RISC-V verification

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on-the-fly instruction stream generation part of → 90% 2e

On-the-fly instruction stream generation is a specific form of instruction stream generation done during simulation.

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CITATIONS

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[1] c1: The described verification approach aims to generate an endless, unrestricted instruction stream and compare RTL core and ISS behavior on observable architectural state such as register updates.

[2] c2: RISC-V has mandatory base integer instruction sets, optional single-letter extensions, 32 general-purpose registers in RV32I, and instruction classes such as computational, load/store, and branch/jump.

[3] c3: The unrestricted approach supports memory-access instructions, jump instructions including self-loops from on-the-fly generation, and special RISC-V CSR access instructions.

[4] c4: The baseline generation algorithm fully randomizes generated instructions, and a fully random 32-bit word is most likely an illegal instruction.

[5] c5: A guided modification injects a random instruction opcode to create a valid instruction while keeping instruction fields randomized, helping ensure many legal instructions are considered.

[6] c6: RTL prefetch, jumps, and traps make it difficult to feed the same unrestricted instruction stream to the RTL core and ISS because prefetched instructions may not execute and the ISS may fetch a different PC sequence.

[7] c7: The instruction matching algorithm keeps a queue of pending RTL-fetched instructions with PCs and matches ISS fetches by PC and expected instruction, reporting a mismatch if no match is found.

[8] c8: A core adapter observes pipeline signal changes, detects completed instructions, preserves correct order for illegal instructions, and provides RTL register values for comparison with the ISS.

[9] c9: RISC-V Torture Test is a Scala-based randomized instruction-sequence-template framework, and approaches using predefined instruction-sequence building blocks are described as coverage-limited and lacking support for illegal instructions or exceptions.

[10] c10: Coverage-guided fuzzing for ISS-level verification loosens some instruction-stream generation restrictions but has problems with branches/jumps, platform-dependent CSR and memory accesses, and comparatively small test suites.

[11] c11: RISC-V DV uses constrained-random descriptions to continuously generate RISC-V instruction streams as test cases and supports features such as ISA extensions and CSR testing, but its generated streams are restricted to avoid infinite loops and platform-dependent memory accesses.