Instruction Stream Generation
TechniqueInstruction Stream Generation is a test-generation technique for processor verification in which streams of instructions are produced and supplied to a processor model, simulator, or RTL core. In the cited RISC-V cross-level verification evidence, the stated goal is to generate an endless and unrestricted instruction stream for co-simulation, with the RTL core and instruction-set simulator (ISS) expected to behave identically in their observable architectural state, especially register updates. Generation begins from a fully randomized 32-bit word and layers on opcode injection, field mutations, and instruction sequences to bias output toward legal and interesting cases. Generated instructions are matched against the ISS using a pending (PC, instruction) queue, while a core adapter observes RTL pipeline signals to detect instruction completion. The article also contrasts this approach with RISC-V Torture, ISS-level coverage-guided fuzzing, and the open-source riscv-dv tool, and describes how the technique is positioned in industry CPU verification curricula.
First seen 5/25/2026
Last seen 9/30/2026
Evidence 11 chunks
Wiki v4
WIKI
Overview
Instruction Stream Generation is a test-generation technique for processor verification in which streams of instructions are produced and supplied to a processor model, simulator, or RTL core. In the cited RISC-V cross-level verification evidence, the stated goal is to generate an endless and unrestricted instruction stream for co-simulation, with the RTL core and instruction-set simulator (ISS) expected to behave identically in their observable architectural state, especially register updates. [c1] [c2]
Role in RISC-V verification and training
NEIGHBORHOOD
2 nodes · 2 edgesgraph · Instruction Stream Generation · depth=1
RELATIONSHIPS
5 connectionsriscv-dv provides an instruction stream generation flow within a UVM-based DV environment and is used to generate tests for RTL simulation.
On-the-fly instruction stream generation is a specific form of instruction stream generation done during simulation.
Instruction-stream generation creates data dependency scenarios as part of useful generated interactions.
Instruction-stream generation includes privilege transitions as part of generated interaction scenarios.
The description mentions instruction stream generation alongside the open-source tool riscv-dv, indicating the technique employs the tool.
LINKED ENTITIES
2 linksriscv-dv IMPLEMENTS Extracted graph relationship
Ibex REFERENCED_BY The cited Imperas slides present Ibex as a case study for the OpenHW RISC-V DV flow that exercises instruction stream generation. Ibex is not provided as a related entity, but the evidence explicitly supports its connection to the instruction stream generation verification flow.
CITATIONS
17 sources17 citations — click to expand
[1] Instruction stream generation produces an endless and unrestricted instruction stream for co-simulation, with the RTL core and ISS expected to behave identically in their observable architectural state, especially register updates. Efficient Cross-Level Testing for RISC-V Processor Verification (FDL 2020)
[2] RISC-V includes mandatory base integer instruction sets such as RV32I, RV64I, RV128I plus optional extensions such as M and C; instructions are grouped into computational, load/store, and branch/jump classes. The RISC-V Software Ecosystem (DEV Community)
[3] Unrestricted generation can include legal and illegal encodings; the approach supports memory-access instructions, jump instructions including self-loops from on-the-fly generation, and special RISC-V CSR access instructions. On-Demand recordings access | Part 1: Introduction to CPU and CPU Verification
[4] Industry training material lists Instruction Stream Generation alongside riscv-dv as part of an introductory CPU and CPU verification curriculum. On-Demand recordings access | Part 1: Introduction to CPU and CPU Verification
[5] A broader RISC-V verification training programme lists instruction stream generation among the topics of a follow-on course on best-practice CPU and SoC verification. The RISC-V Software Ecosystem (DEV Community)
[6] Custom-instruction verification requires extending the generator with constraints and surrounding-context stimulus such as data dependencies, immediate consumers, rd/rs aliasing, branches around the instruction, exceptions/interrupts, back-to-back custom instructions, transitions between custom and standard instructions, privilege transitions, and memory-system activity. Verifying a custom RISC-V instruction (Alpinum Consulting blog)
[7] The baseline generator fully randomizes 32-bit words; a fully random 32-bit word is most likely an illegal instruction because of the larger state space of illegal instructions. Efficient Cross-Level Testing for RISC-V Processor Verification (FDL 2020)
[8] Opcode injection (98% probability), field mutation (20% probability), and instruction sequence start (1% probability) are layered on top of a fully randomized 32-bit word to steer generation toward legal and interesting cases. Efficient Cross-Level Testing for RISC-V Processor Verification (FDL 2020)
[9] Field mutation rules inject special immediate values such as {MIN, -1, 0, 1, MAX}, mutate RD to zero, make RD equal to RS1 and/or RS2, make RS1 equal to RS2, and mutate the CSR selector field to a supported CSR. Efficient Cross-Level Testing for RISC-V Processor Verification (FDL 2020)
[10] The combined instruction generation algorithm optionally starts a sequence (1%), otherwise generates a random 32-bit word, then injects a random valid opcode (98%) and applies a random field mutation (20%) before returning a single instruction. Efficient Cross-Level Testing for RISC-V Processor Verification (FDL 2020)
[11] Unrestricted instruction streams introduce a synchronization problem when the same stream must be supplied to both an RTL core and an ISS; an instruction matching algorithm stores generated instructions with their PCs in a queue searched by the ISS fetch path for matching (PC, instruction) pairs. Efficient Cross-Level Testing for RISC-V Processor Verification (FDL 2020)
[12] A core adapter observes internal core signal changes, especially pipeline signals, to detect instruction completion in a pipelined RTL core while preserving correct order for illegal instructions, despite pipeline flushes, jumps, traps, and multi-cycle operations. Efficient Cross-Level Testing for RISC-V Processor Verification (FDL 2020)
[13] riscv-dv supports custom processor targets, user extensions, additional instruction streams, directed assembly/C tests, ISS-based co-simulation, multiple instruction-set simulators, and instruction-generation coverage, and restricts generated streams to avoid infinite loops and platform-dependent memory access operations. Verifying a custom RISC-V instruction (Alpinum Consulting blog)
[14] The OpenHW RISC-V DV flow uses a UVM environment with a RISC-V reference model: a random instruction generator compiles programs with GCC into a test-program environment that drives the CORE-V CV32/64 RTL and an Imperas reference model in a step-and-compare flow, with reuse of assertions from formal verification. Imperas verification RISC-V Global Forum 2020 v3 (slides)
[15] lowRISC Ibex is a small 32-bit RISC-V CPU core (RV32IMC/EMC) with a two-stage pipeline, previously known as zero-risky (PULP), exposing a prefetch buffer, compressed-instruction decoder, ALU, multiplier/divider, CSR module, and load/store unit with a debug request interface and 32-bit instruction/data memory interfaces. Imperas verification RISC-V Global Forum 2020 v3 (slides)
[16] RISC-V Torture is described as a Scala-based framework generating tests from randomized instruction-sequence templates, supporting several RISC-V ISA extensions but with limited coverage and no support for illegal instructions or exceptions. Efficient Cross-Level Testing for RISC-V Processor Verification (FDL 2020)
[17] Coverage-guided fuzzing at the ISS level loosens some instruction-stream generation restrictions but has problems with branches and jumps, platform-dependent CSR and memory accesses, and produces comparatively small test suites. Efficient Cross-Level Testing for RISC-V Processor Verification (FDL 2020)