opcode injection

Technique

Opcode injection is a test-generation technique for processor verification in which a random valid instruction opcode is inserted into an otherwise randomized instruction word. In the cited RISC-V cross-level verification approach, it helps produce legal instructions while preserving randomized instruction fields, counteracting the tendency of fully random 32-bit words to encode illegal instructions.

First seen 5/26/2026

Last seen 5/30/2026

Evidence 2 chunks

Wiki v1

WIKI

Overview

Opcode injection is used in an instruction stream generator to turn a fully randomized instruction word into a more useful test instruction. The technique injects a random valid instruction opcode while leaving the remaining instruction fields randomized. This creates a valid instruction form without fully constraining operands, immediates, or other fields.

The cited RISC-V verification work presents opcode injection as the first modification to a baseline generator that otherwise fully randomizes generated instructions. The modification is described as simple, generic, and effective, and as important for ensuring that many legal instructions are considered during testing.

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RELATIONSHIPS

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Efficient Cross-Level Testing for Processor Verification: A RISC-V Case-Study ← uses 100% 2e

The paper uses opcode injection as a modification to the instruction generation.

on-the-fly instruction stream generation ← uses 100% 1e

On-the-fly instruction stream generation uses opcode injection to create valid instructions.

instruction generation algorithm ← uses 100% 1e

The instruction generation algorithm uses opcode injection.

LINKED ENTITIES

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RISC-V applies_to The evidence describes opcode injection and field mutation rules derived from the RISC-V instruction format and applies the approach to a RISC-V core.

CITATIONS

7 sources

7 citations — click to expand

[1] Opcode injection inserts a random valid instruction opcode into an otherwise randomized instruction word while keeping instruction fields randomized.

[2] Opcode injection is motivated by the fact that fully random 32-bit instruction words are most likely illegal because the illegal-instruction state space is significantly larger.

[3] The evidence example injects the ADDI opcode into a fully randomized 32-bit instruction word, producing a randomized ADDI instruction.

[4] The cited instruction generator creates a random 32-bit word and injects a random valid opcode with 98% probability.

[5] Field mutation may follow opcode injection, with the cited algorithm applying a random field mutation with 20% probability.

[6] The cited field mutation rules are derived from the RISC-V instruction format and include special immediate values, register-structure mutations, and CSR selector mutation.

[7] The broader verification setup uses an instruction stream generator intended to generate an endless and unrestricted instruction stream, and the overall approach was applied to a pipelined 32-bit industrial RISC-V TGF series core implemented in SpinalHDL.