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STIMSMITH

Instruction Stream Generation

Concept

Instruction stream generation is the creation of processor instruction sequences used as verification test cases or as input streams for co-simulation. In the provided RISC-V processor-verification evidence, instruction streams may be generated by constrained-random or template-based tools, but the cited cross-level testing approach emphasizes an endless instruction stream without restrictions on generated instructions, including memory accesses, jumps such as self-loops, and special CSR accesses.

First seen 5/26/2026
Last seen 6/7/2026
Evidence 25 chunks
Wiki v2

WIKI

Overview

Instruction stream generation is the production of instruction sequences used to exercise processor models during verification. In the cited RISC-V verification context, generated instruction streams can serve as individual test cases, as in RISC-V DV, or as an endless stream used to feed both an RTL core and an instruction set simulator (ISS) in co-simulation [instruction-streams-as-test-inputs].

Use in cross-level co-simulation

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NEIGHBORHOOD

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RELATIONSHIPS

6 connections
MorFuzz ← implements 100% 4e
MorFuzz uses runtime information to generate diverse and meaningful instruction streams.
Translation Buffer ← uses 100% 2e
The Translation Buffer transforms test vectors into endless instruction streams.
on-the-fly instruction stream generation ← uses 90% 2e
On-the-fly instruction stream generation implements the general concept of instruction stream generation.
Efficient Cross-Level Testing for Processor Verification: A RISC-V Case-Study ← uses 95% 2e
The paper's approach is centered around instruction stream generation for processor verification.
MorFuzz ← uses 100% 2e
MorFuzz generates diverse and meaningful instruction streams using morphing.
Examiner ← uses 100% 1e
Examiner generates instruction streams to be fed into its differential testing engine.

LINKED ENTITIES

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on-the-fly instruction stream generation USES Extracted graph relationship
Efficient Cross-Level Testing for Processor Verification: A RISC-V Case-Study USES Extracted graph relationship

CITATIONS

12 sources
12 citations — click to expand
[1] instruction-streams-as-test-inputs Efficient Cross-Level Testing for
[2] same-stream-challenge Efficient Cross-Level Testing for
[3] architectural-equivalence Efficient Cross-Level Testing for
[4] unrestricted-endless-stream Efficient Cross-Level Testing for
[5] supported-instruction-classes Efficient Cross-Level Testing for
[6] prefetch-matching-problem Efficient Cross-Level Testing for
[7] pending-instruction-queue Efficient Cross-Level Testing for
[8] implementation-challenges Efficient Cross-Level Testing for
[9] completion-detection Efficient Cross-Level Testing for
[10] template-based-limitations Efficient Cross-Level Testing for
[11] iss-fuzzing-limitations Efficient Cross-Level Testing for
[12] riscv-dv-generation Efficient Cross-Level Testing for