cross-level testing

Concept

Cross-level testing is a processor-verification approach that co-simulates an RTL core with a higher-level reference model, such as an Instruction Set Simulator, and compares their results instruction by instruction.

First seen 5/30/2026

Last seen 5/30/2026

Evidence 2 chunks

Wiki v1

WIKI

cross-level testing

Cross-level testing is a simulation-based processor-verification approach in which a Register-Transfer Level (RTL) processor implementation is checked against a higher-level reference model. In the RISC-V case study described by Herdt, Große, Jentzsch, and Drechsler, an Instruction Set Simulator (ISS) is used as the reference model for the RTL core under test in a tightly coupled cross-level co-simulation setting. The testbench feeds the generated instruction stream to both the ISS and the RTL core and compares the results after each executed instruction, so RTL errors can be detected immediately when they occur. [C1]

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NEIGHBORHOOD

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graph · cross-level testing · depth=1

RELATIONSHIPS

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on-the-fly instruction stream generation uses → 95% 2e

Cross-level testing generates instructions on-the-fly.

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on-the-fly instruction stream generation USES Extracted graph relationship

CITATIONS

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4 citations — click to collapse

[1] C1: Cross-level testing co-simulates an ISS reference model with an RTL core and compares results after each executed instruction. Efficient Cross-Level Testing for Processor Verification: A RISC-V Case-Study

[2] C2: The cited cross-level testing approach generates an endless instruction stream and evolves it on-the-fly during simulation without restrictions on generated instructions. Efficient Cross-Level Testing for Processor Verification: A RISC-V Case-Study

[3] C3: Extensive RTL processor verification is crucial; simulation-based methods are prevalent due to ease of use and scalability but require efficient test generation for thorough verification. Efficient Cross-Level Testing for Processor Verification: A RISC-V Case-Study

[4] C4: The RISC-V case study applied the approach to the 32-bit pipelined MINRES TGF core, found several serious bugs, and reported more than 200 million processed instructions per hour on a standard laptop. Efficient Cross-Level Testing for Processor Verification: A RISC-V Case-Study