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cross-level testing

Concept WIKI v1 · 5/30/2026

Cross-level testing is a processor-verification approach that co-simulates an RTL core with a higher-level reference model, such as an Instruction Set Simulator, and compares their results instruction by instruction.

cross-level testing

Cross-level testing is a simulation-based processor-verification approach in which a Register-Transfer Level (RTL) processor implementation is checked against a higher-level reference model. In the RISC-V case study described by Herdt, Große, Jentzsch, and Drechsler, an Instruction Set Simulator (ISS) is used as the reference model for the RTL core under test in a tightly coupled cross-level co-simulation setting. The testbench feeds the generated instruction stream to both the ISS and the RTL core and compares the results after each executed instruction, so RTL errors can be detected immediately when they occur. [C1]

Workflow

A cross-level testing setup for processor verification can be summarized as follows:

  1. Generate an instruction stream. The cited RISC-V approach generates an endless instruction stream and evolves it on-the-fly during simulation, without restrictions on the generated instructions. [C2]
  2. Run both abstraction levels. The same instruction stream is executed by the ISS reference model and by the RTL core under test in a tightly coupled co-simulation. [C1]
  3. Compare after each instruction. The testbench compares the results after every executed instruction, enabling immediate detection of mismatches in the RTL implementation. [C1]

Role in processor RTL verification

Cross-level testing is motivated by the need for extensive RTL processor verification: the cited work notes that RTL verification is crucial to avoid bugs and that simulation-based methods remain prevalent because of their ease of use and scalability. However, simulation-based verification also requires efficient test-generation methods to achieve thorough verification. [C3]

RISC-V case-study evidence

The cited paper applies cross-level testing to processor verification targeting the RISC-V ISA. In its reported case study, the approach was used on the 32-bit pipelined RISC-V core of the MINRES The Good Folk (TGF) Series. The authors report that the approach found several serious bugs, and also report efficiency of more than 200 million processed instructions per hour on a standard laptop. [C4]

Relationship to on-the-fly instruction stream generation

The RISC-V approach explicitly uses on-the-fly instruction stream generation: it evolves the instruction stream during simulation and feeds that stream into both the ISS and the RTL core. [C2]

LINKED ENTITIES

1 links
on-the-fly instruction stream generation USES

CITATIONS

4 sources
4 citations
[1] C1: Cross-level testing co-simulates an ISS reference model with an RTL core and compares results after each executed instruction. Efficient Cross-Level Testing for Processor Verification: A RISC-V Case-Study
[2] C2: The cited cross-level testing approach generates an endless instruction stream and evolves it on-the-fly during simulation without restrictions on generated instructions. Efficient Cross-Level Testing for Processor Verification: A RISC-V Case-Study
[3] C3: Extensive RTL processor verification is crucial; simulation-based methods are prevalent due to ease of use and scalability but require efficient test generation for thorough verification. Efficient Cross-Level Testing for Processor Verification: A RISC-V Case-Study
[4] C4: The RISC-V case study applied the approach to the 32-bit pipelined MINRES TGF core, found several serious bugs, and reported more than 200 million processed instructions per hour on a standard laptop. Efficient Cross-Level Testing for Processor Verification: A RISC-V Case-Study