instruction sequence generation

Technique

Instruction sequence generation is a randomized processor-test generation technique in which a generator emits a fixed-length group of instructions designed to perform a specific task, rather than only emitting independent random instructions. In the provided RISC-V verification evidence, sequences are used alongside opcode injection and field mutation to create targeted randomized tests such as large-immediate loads, compute chains, and CSR-access sequences.

First seen 5/26/2026

Last seen 5/30/2026

Evidence 2 chunks

Wiki v1

WIKI

Overview

Instruction sequence generation is described as a modification to random instruction generation for RISC-V processor verification. A sequence consists of a fixed number of instructions that are designed to perform a specific task and can be randomized. This lets the generator create multi-instruction behaviors that a single instruction may not express directly. [C1]

Role in the generator

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RELATIONSHIPS

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Efficient Cross-Level Testing for Processor Verification: A RISC-V Case-Study ← uses 100% 2e

The paper uses instruction sequence generation as a third modification to guide test generation.

on-the-fly instruction stream generation ← uses 100% 1e

On-the-fly instruction stream generation uses instruction sequences designed to perform specific tasks.

instruction generation algorithm ← uses 100% 1e

The instruction generation algorithm incorporates sequence generation.

LINKED ENTITIES

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opcode injection used_with The instruction generation algorithm described in the evidence uses valid opcode injection alongside instruction sequence generation.

CITATIONS

10 sources

10 citations — click to expand

[1] Instruction sequence generation creates fixed-number instruction sequences designed for a specific task and capable of randomization.

[2] The algorithm continues an active sequence if one is incomplete, otherwise starts a random new sequence with 1% probability, and otherwise generates a single independent instruction.

[3] Independent instruction generation starts from a randomized 32-bit instruction word, injects a valid opcode with 98% probability, and applies a random field mutation with 20% probability.

[4] A large-immediate load sequence can use two RISC-V instructions because one immediate field is not large enough to load an arbitrary register value; the target register and load value are randomized.

[5] A compute-chain sequence feeds one instruction result into the next instruction source register while randomizing the operation and operand registers.

[6] A CSR access sequence performs randomized CSR access and writes the CSR value into a normal register for comparison with the ISS register.

[7] Pure randomization tends to generate illegal instructions because illegal instructions have a significantly larger state space; valid opcode injection is used to address this.

[8] Field-mutation rules include special immediate values, register-field relationships, zero-register handling, and CSR selector mutation to a supported CSR.

[9] The reported implementation applied the approach to a pipelined 32-bit industrial RISC-V TGF series core using SpinalHDL-generated Verilog RTL, Verilator, a SystemC co-simulation testbench, and a 32-bit RISC-V ISS from the open-source RISC-V VP.

[10] Instruction sequences support multi-instruction verification scenarios such as large-immediate loading, compute chains, and CSR-state comparison through a normal register.