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TLM (Transaction Level Modeling)

Concept WIKI v1 · 5/26/2026

TLM (Transaction Level Modeling) is presented in the evidence as a SystemC-associated modeling approach that abstracts communication into transactions, commonly for high-level algorithmic models. A TLM transaction object carries a command such as read or write, a data payload, and an address, and can be used to provide a unified memory abstraction across RTL and ISS components in co-simulation.

Overview

TLM (Transaction Level Modeling) is described as part of the relevant background for SystemC-based co-simulation. The evidence states that SystemC in combination with TLM is an industry-proven modeling standard for building designs at different levels of abstraction. In that setting, communication can be implemented either with signals, which are commonly used for RTL models, or abstracted using TLM transactions, which are commonly used for high-level algorithmic models.

Transaction structure

A TLM transaction object essentially consists of:

  • a command, such as read or write;
  • the data, also described as the payload; and
  • the address.

In the memory-access example, the memory receives a transaction object named gp, identified as the TLM generic payload type. The memory obtains the address, access length, and data pointer from this transaction object. It then uses the TLM command to decide whether to perform a data read or a data write operation.

Use in memory interfaces

The evidence describes a memory interface based on TLM in which read and write behavior is driven by the transaction command. For read access, bytes are read from memory into the transaction payload. For write access, bytes from the transaction payload are written into memory.

In a processor-verification co-simulation testbench, memory interfaces translate back and forth between RTL core signals and TLM transactions. The cited work uses TLM transactions to provide a unified memory abstraction for both an RTL core and an instruction-set simulator (ISS) based on a common standard.

Role in SystemC co-simulation

The co-simulation testbench described in the evidence is implemented in SystemC and uses TLM. SystemC itself is described as a C++ class library with an event-driven simulation kernel. Designs are structured with modules, behavior is modeled in processes triggered by events, and process execution is non-preemptive until the process finishes or actively suspends itself.

Within the described testbench, the RTL core is driven by a clock signal and has separate instruction and data memory interfaces. The RTL-facing interfaces translate RTL signals to and from TLM transactions, while the ISS side also uses separate memory interfaces. This allows memory behavior to be represented through the same transaction-level abstraction on both sides of the co-simulation.

LINKED ENTITIES

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SystemC used_with

CITATIONS

6 sources
6 citations
[1] SystemC with TLM is an industry-proven modeling standard for designs at different levels of abstraction.
[2] Communication can be implemented using signals for RTL models or abstracted using TLM transactions for high-level algorithmic models.
[3] A TLM transaction object consists essentially of a command such as read or write, the data payload, and the address.
[4] In the example memory interface, a TLM generic payload transaction named gp supplies address, access length, and data pointer, and the command determines whether read or write operations are performed.
[5] In the described co-simulation testbench, memory interfaces translate between RTL core signals and TLM transactions, enabling a unified memory abstraction for the RTL core and ISS.
[6] The referenced co-simulation testbench is implemented in SystemC and uses TLM.