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MINRES The Good Folk (TGF) Series RTL core

Tool

The TGF Series RTL core is described in the supplied evidence as a pipelined industrial RISC-V RTL core evaluated with a cross-level co-simulation verification approach. The verification setup used a core adapter to observe pipeline-internal activity, detect completed instructions, preserve ordering around illegal instructions, expose RTL register values, and match the RTL instruction stream against an ISS despite prefetching, jumps, traps, and pipeline stalls.

First seen 5/26/2026
Last seen 5/30/2026
Evidence 6 chunks
Wiki v1

WIKI

Overview

The MINRES The Good Folk (TGF) Series RTL core is identified in the evidence as a pipelined industrial RISC-V TGF series core used as the RTL design under test in a cross-level processor-verification setup. The reported verification approach was effective at finding several serious bugs in the core and processed more than 200 million instructions per hour. [CITATION: TGF core verification result]

Verification context

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RELATIONSHIPS

7 connections
The paper presents a case study on verifying the MINRES TGF RTL core.
pipeline ← part of 90% 2e
The pipeline is part of the MINRES TGF Series RTL core and introduces challenges for instruction matching.
MINRES Technologies GmbH published by → 95% 2e
MINRES TGF Series RTL core is a product of MINRES Technologies GmbH.
MINRES Technologies GmbH authored by → 95% 2e
The TGF Series RTL core is developed by MINRES Technologies GmbH.
pipeline implements → 100% 1e
The TGF Series RTL core is a pipelined processor.
RISC-V ISA implements → 100% 1e
The TGF Series RTL core implements the RV32I RISC-V ISA.
RV32I implements → 100% 1e
The MINRES TGF RTL core implements the RV32I ISA with machine mode CSRs.

CITATIONS

8 sources
8 citations — click to expand
[1] TGF core verification result
[2] unrestricted instruction stream and architectural-state comparison
[3] instruction-completion detection challenge
[4] pipeline flush and multi-cycle delay behavior
[5] core adapter functions
[6] RTL and ISS instruction-stream divergence
[7] pending-instruction queue matching algorithm
[8] no direct completed-instruction feed to ISS