Overview
The MINRES The Good Folk (TGF) Series RTL core is identified in the evidence as a pipelined industrial RISC-V TGF series core used as the RTL design under test in a cross-level processor-verification setup. The reported verification approach was effective at finding several serious bugs in the core and processed more than 200 million instructions per hour. [CITATION: TGF core verification result]
Verification context
The evidence describes a co-simulation setup in which an RTL core and an instruction set simulator (ISS) are expected to behave identically with respect to observable architectural state, specifically register updates. The approach generates an endless instruction stream without restrictions, supporting memory-access instructions, jump instructions including self-loops, and special RISC-V CSR access instructions. [CITATION: unrestricted instruction stream and architectural-state comparison]
Pipeline-observation challenge
A key implementation challenge for the TGF Series RTL core is that the pipelined RTL core does not provide a single signal that can be queried to determine that an instruction has completed. Illegal instructions may bypass pipeline stages depending on where they are identified as illegal, and they may not trigger normal register write-back notifications. In addition, an illegal instruction cannot simply be considered complete at detection time because legal instructions ahead of it in the pipeline must complete first to preserve instruction order. [CITATION: instruction-completion detection challenge]
The pipeline can also be flushed by jumps and traps, or become stuck at different stages; the evidence gives shifting as an example of an operation that can take multiple cycles. These behaviors can introduce delays and gaps that must be accounted for when deciding when an instruction has completed. [CITATION: pipeline flush and multi-cycle delay behavior]
Core adapter
To hide implementation details of the TGF Series RTL core and provide a clean testing interface, the verification setup uses a core adapter. The adapter observes internal signal changes, especially pipeline activity, and notifies the test controller whenever the RTL core completes an instruction. It also preserves correct ordering in the presence of illegal instructions and provides access to RTL register values so they can be compared with the ISS. [CITATION: core adapter functions]
Instruction-stream matching
The evidence explains that feeding the same instruction stream to the RTL core and ISS requires special handling because the RTL core can prefetch several instructions due to its pipeline. Prefetched instructions might not execute if a jump or trap occurs, causing the ISS to fetch a different sequence of program counters than the RTL core. Short jumps can also cause the RTL core to fetch a new instruction before the ISS has fetched the corresponding instruction. [CITATION: RTL and ISS instruction-stream divergence]
The described solution keeps a queue of pending instructions that have been fetched by the RTL core but not yet consumed by the ISS. Each queued entry stores both the generated instruction and its program counter. The setup uses the core adapter to extract the last completed RTL instruction and passes it, together with the ISS program counter, to fetch the next ISS instruction. The queue is searched for a matching program counter and expected instruction; if a match is found, the instruction is returned, otherwise a mismatch is reported between the RTL core and ISS. [CITATION: pending-instruction queue matching algorithm]
The evidence explicitly notes that completed instructions from the core adapter are not directly fed into the ISS, because doing so would compromise the test approach by relying on the correctness of instruction propagation in the RTL core, which is the component under test. [CITATION: no direct completed-instruction feed to ISS]
Verification outcome
The reported approach found several serious bugs in the pipelined industrial RISC-V TGF series core and achieved more than 200 million processed instructions per hour. Future-work items mentioned in the evidence include parallelized test sessions with different random seeds, FPGA-based acceleration, interrupt-interface testing synchronized with instruction-stream co-simulation, additional RISC-V ISA-extension evaluation, and new RTL-aware coverage metrics with execution feedback. [CITATION: TGF core verification result]