Trap handling
ConceptTrap handling in the cited RISC-V evidence is represented by generated trap-handler code, including an mtvec_handler section with exception and interrupt handlers, register save support via push_gpr_to_kernel_stack, and trap return through the MRET instruction.
First seen 5/26/2026
Last seen 5/30/2026
Evidence 4 chunks
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Overview
In the provided RISC-V evidence, trap handling is described through generated assembly-program infrastructure and verification results. The riscv_asm_program flow selects an mtvec_handler section that contains an exception_handler and an interrupt_handler, and it calls push_gpr_to_kernel_stack() to push general-purpose registers to the stack for trap handling.
Handler setup in generated programs
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3 connectionspush_gpr_to_kernel_stack implements trap handling by pushing GPRs to the kernel stack.
The paper tests trap handling as part of its comprehensive verification.
Trap handling is part of the Machine mode in the RISC-V privileged architecture.
LINKED ENTITIES
1 linksCITATIONS
5 sources5 citations — click to expand
[1] The generated RISC-V program flow calls push_gpr_to_kernel_stack() to push general-purpose registers to the stack for trap handling and selects an mtvec_handler section containing exception_handler and interrupt_handler definitions. RISC-V source class riscv_asm_program_gen, the brain behind ...
[2] riscv_asm_program_gen and associated helpers generate full RISC-V assembly programs with randomized instructions and randomized GPR selections. RISC-V source class riscv_asm_program_gen, the brain behind ...
[3] MRET is a special RISC-V instruction used to return from the trap handler, and a reported bug caused MRET to continue at the wrong instruction for sequences involving multiple MRET and illegal instructions. [PDF] Efficient Cross-Level Testing for Processor Verification: A RISC-V ...
[4] The cross-level testing approach uses on-the-fly instruction stream generation and unrestricted instruction sequences to expose corner-case bugs involving irregular control flow, including tight loops and traps. [PDF] Efficient Cross-Level Testing for Processor Verification: A RISC-V ...
[5] A reference ISS bug incorrectly set MTVAL when executing a compressed instruction considered an illegal instruction. [PDF] Efficient Cross-Level Testing for Processor Verification: A RISC-V ...