machine learning-based test generation

Technique

Machine learning-based test generation is referenced in the evidence as an alternative approach for instruction-stream generation in processor verification. In the cited RISC-V RTL verification context, such approaches are grouped with coverage-guided generation using Bayesian networks and fuzzing, but are described as either not designed for RTL verification, imposing restrictions on generated instruction streams, or not targeting the RISC-V ISA.

First seen 5/26/2026

Last seen 5/26/2026

Evidence 1 chunks

Wiki v1

WIKI

Overview

Machine learning-based test generation refers here to a class of alternative test-generation approaches discussed in the context of instruction-stream generation for processor verification. The evidence places it alongside coverage-guided test generation based on Bayesian networks and fuzzing as one of several alternatives to model-based and constraint-solving approaches for processor test generation. [C1]

Use in processor verification context

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RELATIONSHIPS

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Efficient Cross-Level Testing for Processor Verification: A RISC-V Case-Study ← mentions 90% 1e

The paper mentions machine learning techniques as an alternative approach to test generation.

LINKED ENTITIES

1 links

Instruction Stream Generation application_area The evidence frames machine learning techniques as alternative approaches proposed for instruction-stream generation in processor verification.

CITATIONS

5 sources

5 citations — click to expand

[1] Machine learning techniques are identified as alternative approaches for instruction-stream generation in processor verification. Efficient Cross-Level Testing for Processor Verification: A RISC-V Case-Study

[2] Extensive RTL processor verification is important to avoid bugs, and simulation-based approaches require efficient test generation for thorough verification. Efficient Cross-Level Testing for Processor Verification: A RISC-V Case-Study

[3] The evidence lists model-based constraint-solving approaches, optimized constraint propagation, coverage models, Bayesian-network-based coverage guidance, other machine learning techniques, and fuzzing as approaches related to instruction-stream generation. Efficient Cross-Level Testing for Processor Verification: A RISC-V Case-Study

[4] The cited source states that the alternative approaches including Bayesian networks, other machine learning techniques, and fuzzing are either not designed for RTL verification, impose restrictions on generated instruction streams, or do not target the RISC-V ISA. Efficient Cross-Level Testing for Processor Verification: A RISC-V Case-Study

[5] The contrasted RISC-V cross-level testing approach generates an endless unrestricted instruction stream on the fly and uses an ISS as a reference model in tightly coupled cross-level co-simulation. Efficient Cross-Level Testing for Processor Verification: A RISC-V Case-Study