Randomised Testing of a Microprocessor Model Using SMT-Solver State Generation
PaperA 2014 paper by B. Campbell and I. Stark, published in Formal Methods for Industrial Critical Systems, on randomized testing of a microprocessor model using SMT-solver-based state generation. It is cited in later processor-verification literature as a prominent constraint-solving-based approach for instruction-stream generation.
First seen 5/26/2026
Last seen 5/26/2026
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Randomised Testing of a Microprocessor Model Using SMT-Solver State Generation is a 2014 paper by B. Campbell and I. Stark. It appeared in Formal Methods for Industrial Critical Systems, edited by F. Lang and F. Flammini, on pages 185–199.
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1 connectionsThe paper cites this work as a constraint-solving based test generation approach.
CITATIONS
4 sources4 citations — click to collapse
[1] The paper was authored by B. Campbell and I. Stark and titled “Randomised Testing of a Microprocessor Model Using SMT-Solver State Generation.” Efficient Cross-Level Testing for Processor Verification: A RISC-V Case-Study
[2] The paper appeared in Formal Methods for Industrial Critical Systems, edited by F. Lang and F. Flammini, in 2014, on pages 185–199. Efficient Cross-Level Testing for Processor Verification: A RISC-V Case-Study
[3] The paper is cited as a prominent example of using constraint-solving techniques for instruction-stream generation in processor verification. Efficient Cross-Level Testing for Processor Verification: A RISC-V Case-Study
[4] The later RISC-V verification paper describes model-based instruction-stream generation approaches as separating the test generator from the architecture description. Efficient Cross-Level Testing for Processor Verification: A RISC-V Case-Study