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Control and Status Register (CSR)

Concept

In the provided RISC-V processor-verification evidence, Control and Status Registers (CSRs) are software-visible registers whose legal values and trap behavior are important to privileged-ISA correctness. The cited testing campaign found multiple CSR-related bugs, including incorrect handling of read-only CSRs, unsupported CSR values, trap-status registers, and counter CSRs.

First seen 5/26/2026
Last seen 5/30/2026
Evidence 6 chunks
Wiki v2

WIKI

Overview

A Control and Status Register (CSR) appears in the evidence as software-visible RISC-V state involved in privileged behavior, exception handling, and implementation-capability reporting. The paper notes that, because RISC-V is modular and extensible, software can query CSRs to obtain processor capabilities; therefore, allowing unsupported or reserved CSR values can mislead software about what the implementation supports. [csr-capability-query]

CSR correctness issues observed in testing

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RELATIONSHIPS

2 connections
The paper tests and discusses CSR behavior extensively.
Machine mode (RISC-V privileged architecture) part of → 100% 1e
CSRs form the backbone of the Machine mode privileged architecture description.

CITATIONS

11 sources
11 citations — click to expand
[1] csr-capability-query Efficient Cross-Level Testing for
[2] csr-readonly-write Efficient Cross-Level Testing for
[3] csr-mepc-lower-bits Efficient Cross-Level Testing for
[7] csr-mcause-ebreak Efficient Cross-Level Testing for
[8] csr-counter-writes Efficient Cross-Level Testing for
[9] csr-minstret-write Efficient Cross-Level Testing for
[10] csr-verification-performance Efficient Cross-Level Testing for
[11] csr-cross-level-testing Efficient Cross-Level Testing for