Control and Status Register (CSR)
ConceptIn the provided RISC-V processor-verification evidence, Control and Status Registers (CSRs) are software-visible registers whose legal values and trap behavior are important to privileged-ISA correctness. The cited testing campaign found multiple CSR-related bugs, including incorrect handling of read-only CSRs, unsupported CSR values, trap-status registers, and counter CSRs.
WIKI
Overview
A Control and Status Register (CSR) appears in the evidence as software-visible RISC-V state involved in privileged behavior, exception handling, and implementation-capability reporting. The paper notes that, because RISC-V is modular and extensible, software can query CSRs to obtain processor capabilities; therefore, allowing unsupported or reserved CSR values can mislead software about what the implementation supports. [csr-capability-query]
CSR correctness issues observed in testing
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