Bayesian network-based test generation

Technique

Bayesian network-based test generation is a coverage-guided test generation technique referenced in the context of instruction-stream generation for processor verification. In the provided evidence, it is described as an alternative to model-based and constraint-solving approaches, but the cited comparison notes that such alternative approaches are not aimed at RISC-V ISA testing and are either not designed for RTL verification or impose restrictions on generated instruction streams.

First seen 5/26/2026

Last seen 6/7/2026

Evidence 4 chunks

Wiki v1

WIKI

Overview

Bayesian network-based test generation is identified in the provided evidence as a form of coverage-guided test generation that uses Bayesian networks. It is discussed among approaches for generating instruction streams for processor verification.

Verification context

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RELATIONSHIPS

4 connections

Efficient Cross-Level Testing for Processor Verification: A RISC-V Case-Study ← mentions 90% 1e

The paper mentions Bayesian network-based test generation as a related approach.

coverage-guided test generation ← part of 85% 1e

Bayesian network-based test generation is a form of coverage-guided test generation.

Cross-level processor verification via endless randomized instruction stream generation with coverage-guided aging ← compares with 80% 1e

The paper discusses Bayesian network-based test generation as a related approach

Constrained Random Verification for RISC-V: Overview, Evaluation and Discussion ← mentions 90% 1e

The paper mentions Bayesian network-based test generation as a related approach.

LINKED ENTITIES

1 links

Instruction Stream Generation used_for The evidence discusses Bayesian network-based coverage-guided test generation among approaches proposed for instruction stream generation in processor verification.

CITATIONS

5 sources

5 citations — click to expand

[1] Bayesian network-based test generation is described as coverage-guided test generation based on Bayesian networks. Efficient Cross-Level Testing for Processor Verification: A RISC-V Case-Study

[2] The technique is discussed in the context of instruction stream generation for processor verification. Efficient Cross-Level Testing for Processor Verification: A RISC-V Case-Study

[3] Simulation-based RTL processor verification requires efficient test generation to achieve thorough verification. Efficient Cross-Level Testing for Processor Verification: A RISC-V Case-Study

[4] The cited comparison groups Bayesian-network-based test generation with other machine-learning and fuzzing approaches as alternatives to model-based and constraint-solving test generation. Efficient Cross-Level Testing for Processor Verification: A RISC-V Case-Study

[5] The cited paper states that these alternative approaches are either not designed for RTL verification or restrict generated instruction streams, and that they do not target the RISC-V ISA. Efficient Cross-Level Testing for Processor Verification: A RISC-V Case-Study