Eyck Jentzsch
PersonEyck Jentzsch is documented as a co-author of RISC-V processor-verification papers, including work on cross-level processor verification using endless randomized instruction-stream generation. The cited papers associate him with MINRES Technologies GmbH.
First seen 5/25/2026
Last seen 6/5/2026
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Eyck Jentzsch
Eyck Jentzsch is documented in the available evidence as a co-author in RISC-V processor-verification research. He appears as an author of Cross-Level Processor Verification via Endless Randomized Instruction Stream Generation with Coverage-guided Aging and Efficient Cross-Level Testing for Processor Verification: A RISC-V Case-Study. [1][4]
Affiliation
NEIGHBORHOOD
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3 connections Cross-level processor verification via endless randomized instruction stream generation with coverage-guided aging ← authored by 100% 5e
Eyck Jentzsch is listed as an author of the paper.
Eyck Jentzsch is affiliated with MINRES Technologies GmbH.
Eyck Jentzsch is listed as an author of the paper.
LINKED ENTITIES
3 linksCross-level processor verification via endless randomized instruction stream generation with coverage-guided aging AUTHORED_BY Extracted graph relationship
MINRES Technologies GmbH PART_OF Extracted graph relationship
Efficient Cross-Level Testing for Processor Verification: A RISC-V Case-Study AUTHOR_OF The paper header lists Eyck Jentzsch as one of the authors.
CITATIONS
6 sources6 citations — click to expand
[1] Eyck Jentzsch is listed as an author of Cross-Level Processor Verification via Endless Randomized Instruction Stream Generation with Coverage-guided Aging. Cross-Level Processor Verification via Endless Randomized Instruction Stream Generation with Coverage-guided Aging
[2] The 2022 paper lists Eyck Jentzsch's affiliation as MINRES Technologies GmbH, 85579 Neubiberg, Germany. Cross-Level Processor Verification via Endless Randomized Instruction Stream Generation with Coverage-guided Aging
[3] The 2022 paper proposes RTL processor cross-level verification using an endless randomized coverage-guided instruction stream, an ISS reference model in tight co-simulation, and Coverage-guided Aging. Cross-Level Processor Verification via Endless Randomized Instruction Stream Generation with Coverage-guided Aging
[4] Eyck Jentzsch is listed as an author of Efficient Cross-Level Testing for Processor Verification: A RISC-V Case-Study. Efficient Cross-Level Testing for Processor Verification: A RISC-V Case-Study
[5] The 2020 paper lists Eyck Jentzsch's affiliation as MINRES® Technologies GmbH, Munich, Germany. Efficient Cross-Level Testing for Processor Verification: A RISC-V Case-Study
[6] The 2020 paper proposes cross-level testing for RISC-V processor verification using an endless on-the-fly instruction stream and an ISS reference model in tightly coupled co-simulation, with a case study on the 32-bit pipelined RISC-V core of the MINRES The Good Folk Series that found several serious bugs. Efficient Cross-Level Testing for Processor Verification: A RISC-V Case-Study