Eyck Jentzsch

Eyck Jentzsch is documented in the available evidence as a co-author in RISC-V processor-verification research. He appears as an author of Cross-Level Processor Verification via Endless Randomized Instruction Stream Generation with Coverage-guided Aging and Efficient Cross-Level Testing for Processor Verification: A RISC-V Case-Study. [1][4]

Affiliation

The cited papers associate Jentzsch with MINRES Technologies GmbH. The 2022 paper lists the affiliation as MINRES Technologies GmbH in 85579 Neubiberg, Germany, while the 2020 paper lists MINRES® Technologies GmbH in Munich, Germany. [2][5]

Associated publications

Cross-Level Processor Verification via Endless Randomized Instruction Stream Generation with Coverage-guided Aging

Jentzsch is listed with Niklas Bruns, Vladimir Herdt, and Rolf Drechsler as an author of this paper. The paper proposes a cross-level verification approach for RTL processor verification based on a randomized, coverage-guided instruction stream generator that produces one endless and unrestricted instruction stream evolving at runtime. It uses an Instruction Set Simulator as a reference model in tight co-simulation and applies Coverage-guided Aging to smooth the coverage distribution over time. [1][3]

Efficient Cross-Level Testing for Processor Verification: A RISC-V Case-Study

Jentzsch is also listed with Vladimir Herdt, Daniel Große, and Rolf Drechsler as an author of this paper. The paper proposes an efficient cross-level testing approach for processor verification targeting the RISC-V ISA. It describes generating an endless instruction stream during simulation, using an Instruction Set Simulator as a reference model for the RTL core in tightly coupled cross-level co-simulation, and reports a case study on the 32-bit pipelined RISC-V core of the MINRES The Good Folk Series, where the approach was effective in finding several serious bugs. [4][6]