bayesian network coverage-guided test generation

Technique

Bayesian network coverage-guided test generation is cited in a RISC-V processor-verification survey context as an alternative instruction-stream generation approach. The cited RISC-V cross-level testing paper groups it with machine-learning and fuzzing-based alternatives, noting that such approaches are either not designed for RTL verification or impose instruction-stream restrictions and do not target the RISC-V ISA.

First seen 5/30/2026

Last seen 5/30/2026

Evidence 1 chunks

Wiki v1

WIKI

Overview

Bayesian network coverage-guided test generation is mentioned in the processor-verification literature as an alternative approach for instruction stream generation. In Efficient Cross-Level Testing for Processor Verification: A RISC-V Case-Study, Herdt, Große, Jentzsch, and Drechsler list it alongside other machine-learning and fuzzing-based approaches for processor test generation.

Role in processor-verification test generation

READ FULL ARTICLE →

NEIGHBORHOOD

No graph connections found for this entity yet. It may appear in future ingestion runs.

explore full graph →

RELATIONSHIPS

1 connections

Efficient Cross-Level Testing for Processor Verification: A RISC-V Case-Study ← mentions 90% 1e

The paper mentions bayesian network coverage-guided test generation as a related approach.

LINKED ENTITIES

1 links

Efficient Cross-Level Testing for Processor Verification: A RISC-V Case-Study MENTIONS Extracted graph relationship

CITATIONS

4 sources

4 citations — click to collapse

[1] The technique is mentioned as an alternative instruction-stream generation approach for processor verification. Efficient Cross-Level Testing for Processor Verification: A RISC-V Case-Study

[2] The cited paper groups Bayesian-network-based coverage-guided generation with machine-learning and fuzzing approaches. Efficient Cross-Level Testing for Processor Verification: A RISC-V Case-Study

[3] The cited paper states that these alternative approaches are either not designed for RTL verification or impose restrictions on generated instruction streams and do not target the RISC-V ISA. Efficient Cross-Level Testing for Processor Verification: A RISC-V Case-Study

[4] The RISC-V case-study paper proposes a cross-level RTL verification approach that generates an endless instruction stream on the fly and uses an ISS as a reference model in tightly coupled co-simulation. Efficient Cross-Level Testing for Processor Verification: A RISC-V Case-Study