Overview

Bayesian network coverage-guided test generation is mentioned in the processor-verification literature as an alternative approach for instruction stream generation. In Efficient Cross-Level Testing for Processor Verification: A RISC-V Case-Study, Herdt, Große, Jentzsch, and Drechsler list it alongside other machine-learning and fuzzing-based approaches for processor test generation.

Role in processor-verification test generation

The paper frames instruction stream generation as an important part of simulation-based processor verification, where efficient test generation is needed for thorough verification at the Register-Transfer Level (RTL). Within that landscape, it distinguishes model-based and constraint-based approaches from alternatives that include coverage-guided test generation based on Bayesian networks.

Limitations noted in the cited RISC-V context

In the same discussion, the paper states that these alternative approaches—covering Bayesian-network-based coverage guidance, other machine-learning techniques, and fuzzing—are either not designed for RTL verification or impose restrictions on generated instruction streams. It also states that they do not target the RISC-V ISA.

Relationship to cross-level RISC-V testing

The technique is mentioned as prior or related work in contrast to the paper's proposed cross-level RISC-V verification approach, which generates an endless instruction stream on the fly during simulation and uses an Instruction Set Simulator as a reference model for an RTL core in tightly coupled co-simulation.