Cross-level verification is a processor-verification approach that co-simulates an RTL core under test with a reference instruction-set simulator (ISS), feeds both with the same instruction stream, and checks behavioral equivalence, such as by comparing register values. The provided evidence describes a RISC-V-focused implementation that combines this cross-level co-simulation with coverage-guided fuzzing, deterministic translation of bounded fuzzer inputs into endless instruction streams, runtime limiting, and post-processing of mismatch-triggering tests.

No graph connections found for this entity yet. It may appear in future ingestion runs.