Constrained Random Test Generation
TechniqueConstrained random test generation is a widely adopted stimulus-generation technique for simulation-based verification. The cited literature highlights its core trade-off: randomness improves diversity, but many generated tests repeatedly exercise the same logic and contribute little to late-stage coverage, motivating learned test-selection methods and hybrid intelligent testing approaches.
First seen 5/27/2026
Last seen 6/3/2026
Evidence 8 chunks
Wiki v5
WIKI
Overview
Constrained random test generation is a widely adopted method for generating stimuli in simulation-based verification. In the cited description, randomness provides test diversity, while constraints bias generated tests toward interesting, hard-to-reach, and yet-untested logic; those constraints are typically written manually. The same source notes that unconstrained diversity alone is not enough, because tests often repeatedly exercise the same design logic. [C1]
Main limitation
NEIGHBORHOOD
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11 connections Supervised Learning for Coverage-Directed Test Selection in Simulation-Based Verification ← uses 90% 4e
The paper discusses constrained random test generation as the predominant method for stimuli generation that the proposed approach builds upon.
Constrained-random test generation is used for automated test creation
The paper evaluates constrained random test generation as the baseline approach that has scalability limitations.
RISCV-DV implements constrained-random test generation for RISC-V assembly tests
The hybrid intelligent testing approach is proposed as an improvement over constrained random test generation which requires millions of tests.
Constrained random test generation is a method for generating stimuli in simulation-based verification.
Supervised Learning for Coverage-Directed Test Selection in Simulation-Based Verification ← evaluates 85% 1e
The paper evaluates and contextualises constrained random test generation as the dominant existing approach that coverage-directed test selection improves upon.
RISC-V DV uses constrained-random descriptions to generate instruction streams.
The paper mentions constrained-random test generation as used by RISC-V DV.
The paper discusses constrained random test generation as an existing approach with limitations.
The paper mentions constrained random test generation as a baseline method requiring many tests.
CITATIONS
7 sources7 citations — click to expand
[1] Constrained random test generation is widely adopted in simulation-based verification; randomness provides diversity, but tests often repeatedly exercise the same logic, and constraints are typically written manually to target interesting, hard-to-reach, and yet-untested logic. Supervised Learning for Coverage-Directed Test Selection in Simulation-Based Verification
[2] As verification progresses, most constrained random tests yield little to no effect on functional coverage. Supervised Learning for Coverage-Directed Test Selection in Simulation-Based Verification
[3] Using constrained random test generation for simulation-based hardware verification may require several millions of tests, and the vast majority do not contribute to coverage progress while still consuming verification resources. Hybrid Intelligent Testing in Simulation-Based Verification
[4] If stimulus generation is much cheaper than simulation, the cited work recommends generating many tests and simulating only a selected subset; coverage-directed test selection uses supervised learning from coverage feedback to prioritize tests likely to increase functional coverage and is reported to reduce manual constraint writing, resource use, and coverage-closure time. Supervised Learning for Coverage-Directed Test Selection in Simulation-Based Verification
[5] Hybrid Intelligent Testing combines Coverage-Directed Test Selection and Novelty-Driven Verification and is presented as addressing the limitations of each method to make hardware testing more efficient and effective. Hybrid Intelligent Testing in Simulation-Based Verification
[6] In the cited RISC-V processor-verification example, RISC-V DV generates instruction streams from constrained-random descriptions using SystemVerilog and UVM, provides co-simulation through execution-log comparison, supports ISA extensions and CSR testing, but imposes restrictions to avoid infinite loops and platform-dependent memory accesses and has significant performance overhead due to its generic decoupled framework. Efficient Cross-Level Testing for Processor Verification: A RISC-V Case-Study
[7] The RISC-V case-study cites related instruction-generation approaches including constraint-solving-based model-based generation, frameworks that propagate constraints across multiple instructions, and generators whose coverage models encode constraints over instruction execution paths. Efficient Cross-Level Testing for Processor Verification: A RISC-V Case-Study