Constrained random test generation
TechniqueConstrained random test generation is a widely adopted stimulus-generation technique for simulation-based hardware verification, in which random stimulus is steered by manually or automatically authored constraints to bias tests toward interesting, hard-to-reach logic. Concrete realizations include coverage-point-driven constraint solvers used by RISCV-CTG, SystemVerilog/UVM-based constrained-random generators such as RISC-V DV, and Python-driven constrained-random generators (e.g., the ConfigDrivenV framework) that pair with UVM scoreboards. The cited literature highlights a core trade-off: randomness improves diversity, but as verification progresses most generated tests repeatedly exercise the same logic and contribute little to functional coverage, motivating learned test-selection methods and hybrid intelligent testing approaches.
First seen 5/27/2026
Last seen 9/21/2026
Evidence 29 chunks
Wiki v7
WIKI
Overview
Constrained random test generation is a widely adopted method for generating stimuli in simulation-based verification. In the cited description, randomness provides test diversity, while constraints bias generated tests toward interesting, hard-to-reach, and yet-untested logic; those constraints are typically written manually. The same source notes that unconstrained diversity alone is not enough, because tests often repeatedly exercise the same design logic. [C1]
In the broader verification ecosystem, the term refers to any pipeline in which random stimulus production is narrowed by an explicit specification of what should be tested — a constraint expressed as code, a coverage group, or an external generator — before the stimulus is fed to the design under test (DUT). Several cited works frame constrained random generation as the dominant practical alternative to purely directed testing, which is limited in design-space coverage, and to formal verification, which is limited by state-space explosion. [C7][C4]
NEIGHBORHOOD
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20 connectionsConstrained-random test generation is used for automated test creation
Supervised Learning for Coverage-Directed Test Selection in Simulation-Based Verification ← uses 90% 4e
The paper discusses constrained random test generation as the predominant method for stimuli generation that the proposed approach builds upon.
RISCV-DV uses constrained-random descriptions for instruction stream generation
Stimulus is generated using a constrained-random approach on the Python side.
Python implements the constrained random test generation layer.
The hybrid intelligent testing approach is proposed as an improvement over constrained random test generation which requires millions of tests.
Constrained random test generation is a method for generating stimuli in simulation-based verification.
The paper evaluates constrained random test generation as the baseline approach that has scalability limitations.
IBM GenesysPro is a constrained random test generator implementing constrained random test generation techniques.
Constrained Random Test Generation is applied to verify processors implementing the IBM z/Architecture.
Constrained random test generation is the Python layer component of the two-layer architecture.
Stimuli are generated in a constrained-random fashion for ISA verification.
RISC-V DV uses constrained-random descriptions to generate instruction streams.
Supervised Learning for Coverage-Directed Test Selection in Simulation-Based Verification ← evaluates 85% 1e
The paper evaluates and contextualises constrained random test generation as the dominant existing approach that coverage-directed test selection improves upon.
The paper discusses constrained random test generation as an existing approach with limitations.
The paper mentions constrained random test generation as a baseline method requiring many tests.
CTG is described as similar to a constrained test generator capable of generating tests targeting specific constraints.
Test Generator 110 is a constrained random test generator that implements the constrained random test generation technique.
The Python layer performs constrained-random stimulus creation.
The paper mentions constrained-random test generation as used by RISC-V DV.
LINKED ENTITIES
4 linksConfigDrivenV USES Extracted graph relationship
Python USES Extracted graph relationship
UVM Verification of RISC-V Instruction Set (ICAECA 2024) USES Extracted graph relationship
RISCV-CTG RELATED The previous article documents RISCV-CTG as a concrete realization of constrained random test generation that uses a Coverage Group Format file and the python-constraint CSP solver; this is directly supported by the previous article's source chunks and is consistent with the technique.
CITATIONS
17 sources17 citations — click to expand
[1] Constrained random test generation is one of the most widely adopted methods for generating stimuli for simulation-based verification, where randomness provides test diversity and constraints are typically written manually to bias tests toward interesting, hard-to-reach, and yet-untested logic. Supervised Learning for Coverage-Directed Test Selection in Simulation-Based Verification
[2] Simulation-based hardware verification may require several millions of tests to achieve coverage goals, and the vast majority of those tests do not contribute to coverage progress yet consume verification resources. Hybrid Intelligent Testing in Simulation-Based Verification
[3] Coverage-directed test selection is a supervised-learning method that learns from coverage feedback, biases selection toward tests likely to increase functional coverage, and aims to reduce manual constraint writing, prioritize effective tests, reduce resource consumption, and accelerate coverage closure on a large, real-life industrial hardware design. Supervised Learning for Coverage-Directed Test Selection in Simulation-Based Verification
[4] The Hybrid Intelligent Testing approach combines Coverage-Directed Test Selection with Novelty-Driven Verification to address the limitations of each method and make testing both efficient and effective. Hybrid Intelligent Testing in Simulation-Based Verification
[5] RISCV-CTG implements constrained random test generation by treating each cover-point in a Coverage Group Format (CGF) file as a constraint, using CSP solvers from the python-constraint Python package to find concrete solutions that satisfy the cover-points. RISCV-CTG documentation
[6] Each RISCV-CTG instruction is described by a structured YAML instruction attribute entry fixing XLEN, ISA extension, operation string, format type, legal operand registers, operand values, and an assembly template. RISCV-CTG documentation
[7] RISC-V DV uses SystemVerilog together with UVM to continuously generate RISC-V instruction streams from constrained-random descriptions, supports multiple ISA extensions and CSR testing, and has the disadvantages of needing restrictions to avoid infinite loops and platform-dependent memory accesses, plus significant performance overhead from fully decoupling test generation from co-simulation. RISC-V processor verification survey
[8] The RISC-V Torture Test is a Scala-based model-based framework that generates tests from randomized instruction sequence templates and supports several RISC-V ISA extensions; an alternative model-based approach uses constraint-based specifications for test generation but is limited by pre-defined instruction-sequence building blocks and lacks support for illegal instructions and exceptions; coverage-guided ISS-level fuzzing approaches still suffer from non-terminating test cases and platform-dependent CSR and memory-access operations, producing test-suites of only a few thousand cases. RISC-V processor verification survey
[9] A coverage and constraint-based test generation flow for the RV32F floating-point extension is described as not open-source, limited to 32-bit single precision, and not addressing off-the-shelf RISC-V simulators or alternative FP libraries. FP-RVVTS paper / 2026 review
[10] RISC-V DV initializes FP registers only once at the beginning of a test with special values, restricting operand diversity and consequently FP coverage. FP-RVVTS paper
[11] ConfigDrivenV is a two-layer Python-UVM co-verification framework that integrates Python-based constrained random test generation with a UVM testbench and a self-checking scoreboard, validated on a 16-bit RISC-style processor and a UART controller. ConfigDrivenV: A Python-Integrated UVM Testbench for Automated RTL Verification with Self-Checking Scoreboard – IJERT
[12] The ConfigDrivenV Python generator produces N random CPU instructions by selecting from a defined instruction set, assigning random destination registers (rd ∈ {0,1,2,3}), and generating signed 8-bit immediate values (imm ∈ [−128, +127]) encoded in a 16-bit format (bits [15:12] opcode, bits [9:8] rd, bits [7:0] immediate). ConfigDrivenV: A Python-Integrated UVM Testbench for Automated RTL Verification with Self-Checking Scoreboard – IJERT
[13] ConfigDrivenV reports 100% verification accuracy on correct RTL (PASS=100, FAIL=0) and 100% bug detection effectiveness on deliberately corrupted RTL (PASS=0, FAIL=100) for both the 16-bit RISC-style processor and the UART controller. ConfigDrivenV: A Python-Integrated UVM Testbench for Automated RTL Verification with Self-Checking Scoreboard – IJERT
[14] The ConfigDrivenV paper motivates its Python-fronted approach by noting that industry-grade verification typically uses Cadence Xcelium or Synopsys VCS with full constraint solver support, while academic environments are often constrained to free tools such as ModelSim Starter Edition that lack SystemVerilog randomization, and the framework replaces SystemVerilog randomization with Python-generated test files. ConfigDrivenV: A Python-Integrated UVM Testbench for Automated RTL Verification with Self-Checking Scoreboard – IJERT
[15] The ConfigDrivenV paper cites a 2024 IEEE paper on UVM verification of RISC-V instruction sets that uses constrained random stimulus and functional coverage groups, with results confirming that random instruction generation achieves significantly higher design-space coverage than directed testing. ConfigDrivenV: A Python-Integrated UVM Testbench for Automated RTL Verification with Self-Checking Scoreboard – IJERT
[16] Cited UART verification work reports achieving 100% functional coverage using SystemVerilog-based constrained random verification, with 20 boundary-spanning test vectors described as adequate for UART protocol behavior. ConfigDrivenV: A Python-Integrated UVM Testbench for Automated RTL Verification with Self-Checking Scoreboard – IJERT
[17] ConfigDrivenV cites Chippagi's reusable UVM framework for Power ISA processor cores — which introduced a software predictor model computing expected register states and feeding them to a UVM scoreboard — as the direct academic precedent for its Python golden reference model, demonstrating complete coverage across arithmetic, logical, and memory-access instruction classes. ConfigDrivenV: A Python-Integrated UVM Testbench for Automated RTL Verification with Self-Checking Scoreboard – IJERT