constrained-random test generation

Constrained Random Test Generation

Technique

Constrained random test generation is a widely adopted stimulus-generation technique for simulation-based verification, in which random stimulus generation is steered by manually or automatically authored constraints to bias tests toward interesting, hard-to-reach logic. Concrete realizations include coverage-point-driven constraint solvers such as RISCV-CTG and SystemVerilog/UVM frameworks such as RISC-V DV. The cited literature highlights a core trade-off: randomness improves diversity, but as verification progresses most generated tests repeatedly exercise the same logic and contribute little to functional coverage, motivating learned test-selection methods and hybrid intelligent testing approaches.

First seen 5/27/2026

Last seen 7/16/2026

Evidence 12 chunks

Wiki v6

WIKI

Overview

Constrained random test generation is a widely adopted method for generating stimuli in simulation-based verification. In the cited description, randomness provides test diversity, while constraints bias generated tests toward interesting, hard-to-reach, and yet-untested logic; those constraints are typically written manually. The same source notes that unconstrained diversity alone is not enough, because tests often repeatedly exercise the same design logic. [C1]

Mechanism in practice: coverage-point–driven constraint solving

READ FULL ARTICLE →

NEIGHBORHOOD

No graph connections found for this entity yet. It may appear in future ingestion runs.

explore full graph →

RELATIONSHIPS

12 connections

Supervised Learning for Coverage-Directed Test Selection in Simulation-Based Verification ← uses 90% 4e

The paper discusses constrained random test generation as the predominant method for stimuli generation that the proposed approach builds upon.

Functional Verification of a RISC-V Vector Accelerator ← uses 99% 4e

Constrained-random test generation is used for automated test creation

riscv-dv ← implements 100% 3e

RISCV-DV is an open-source constrained-random generator for RISC-V.

Hybrid Intelligent Testing in Simulation-Based Verification ← evaluates 85% 2e

The paper evaluates constrained random test generation as the baseline approach that has scalability limitations.

Hybrid Intelligent Testing ← compares with 2e

The hybrid intelligent testing approach is proposed as an improvement over constrained random test generation which requires millions of tests.

Stimuli Generation uses → 100% 2e

Constrained random test generation is a method for generating stimuli in simulation-based verification.

RISCV-CTG ← implements 95% 1e

CTG is described as similar to a constrained test generator capable of generating tests targeting specific constraints.

riscv-dv ← uses 100% 1e

RISC-V DV uses constrained-random descriptions to generate instruction streams.

Supervised Learning for Coverage-Directed Test Selection in Simulation-Based Verification ← evaluates 85% 1e

The paper evaluates and contextualises constrained random test generation as the dominant existing approach that coverage-directed test selection improves upon.

Hybrid Intelligent Testing in Simulation-Based Verification ← uses 90% 1e

The paper discusses constrained random test generation as an existing approach with limitations.

Hybrid Intelligent Testing in Simulation-Based Verification ← mentions 1e

The paper mentions constrained random test generation as a baseline method requiring many tests.

Efficient Cross-Level Testing for Processor Verification: A RISC-V Case-Study ← mentions 90% 1e

The paper mentions constrained-random test generation as used by RISC-V DV.

LINKED ENTITIES

1 links

RISCV-CTG IMPLEMENTS Extracted graph relationship

CITATIONS

9 sources

9 citations — click to expand

[1] Constrained random test generation combines randomness for diversity with typically manually written constraints to bias tests toward interesting, hard-to-reach, and yet-untested logic, but tests often repeatedly exercise the same design logic, and as verification progresses most generated tests have little or no effect on functional coverage. Supervised Learning for Coverage-Directed Test Selection in Simulation-Based Verification

[2] RISCV-CTG implements constrained random test generation by consuming a Coverage Group Format (CGF) file of cover-points, treating each cover-point as a constraint, and solving the resulting constraint satisfaction problem with the python-constraint Python package; its internal data flow uses per-instruction YAML attribute entries (xlen, isa, operation, formattype, rs1/rs2/rd_op_data, rs1/rs2_val_data, template) and its capabilities are bounded by the completeness of the CGF. 1. Overview — RISC-V Compatibility Test Generator 0.5.5 documentation

[3] Simulation-based hardware verification using constrained random test generation may require several millions of tests to achieve coverage goals, with the vast majority of tests not contributing to coverage progress while still consuming verification resources. Hybrid Intelligent Testing in Simulation-Based Verification

[4] Coverage-Directed Test Selection is presented as a supervised-learning method that learns from coverage feedback, biases selection toward tests likely to increase functional coverage, and aims to reduce manual constraint writing, prioritize effective tests, reduce resource consumption, and accelerate coverage closure. Supervised Learning for Coverage-Directed Test Selection in Simulation-Based Verification

[5] Hybrid Intelligent Testing combines Coverage-Directed Test Selection with Novelty-Driven Verification to address the individual methods' limitations and make simulation-based testing both efficient and effective. Hybrid Intelligent Testing in Simulation-Based Verification

[6] RISC-V DV (Google) uses SystemVerilog and UVM to continuously generate RISC-V instruction streams from constrained-random descriptions, each stream representing a test case, supports several ISA extensions and CSR testing, and provides a high-level co-simulation interface based on execution-log comparison; its disadvantages include restrictions to avoid infinite loops and platform-dependent memory accesses and significant performance overhead from its generic, fully decoupled test-generation and co-simulation structure. Efficient Cross-Level Testing for RISC-V Processors (FDL 2020)

[7] The cited RISC-V instruction-stream generation survey also describes RISC-V Torture Test as a Scala-based model-based framework using randomized instruction sequence templates, an alternative model-based approach (cited as [11]) that uses constraint-based specification for test generation but is limited by pre-defined building blocks and does not support illegal instructions or exceptions, and ISS-level coverage-guided fuzzing approaches that loosen generation restrictions but still have problems with branches/jumps, platform-dependent CSR/memory access, and produce only a few thousand test cases. Efficient Cross-Level Testing for RISC-V Processors (FDL 2020)

[8] A coverage and constraint-based test generation approach [24] has been proposed specifically for the RV32F floating-point extension on a single RTL processor; the flow is not open-source, is limited to 32-bit single precision, and does not address off-the-shelf RISC-V simulators, alternative FP libraries, or systematic failure-cause analysis. Float Fight - Verifying Floating-Point Behavior in RISC-V Simulators (DATE 2026 LBR)

[9] The open-source constrained-random generator RISCV-DV initializes FP registers only once at the beginning of a test with special values, which limits operand diversity and thus FP coverage. Float Fight - Verifying Floating-Point Behavior in RISC-V Simulators (DATE 2026 LBR)