Overview

Constrained random test generation is a widely adopted method for generating stimuli in simulation-based verification. In the cited description, randomness provides test diversity, while constraints bias generated tests toward interesting, hard-to-reach, and yet-untested logic; those constraints are typically written manually. The same source notes that unconstrained diversity alone is not enough, because tests often repeatedly exercise the same design logic. [C1]

Main limitation

A recurring limitation is diminishing coverage return over time. As verification progresses, most constrained random tests may have little or no effect on functional coverage. One cited abstract further states that simulation-based hardware verification may require several millions of tests to reach coverage goals, while the vast majority of those tests do not contribute to coverage progress and still consume verification resources. [C2][C3]

Responses in the cited literature

One response is to decouple cheap stimulus generation from expensive simulation. When generating stimuli costs much less than simulating them, the cited work argues that a better strategy is to generate many random tests, predict which ones are most effective, and simulate only that subset. In that context, coverage-directed test selection is presented as a supervised-learning method that learns from coverage feedback, biases selection toward tests likely to increase functional coverage, and aims to reduce manual constraint writing, prioritize effective tests, reduce resource consumption, and accelerate coverage closure. [C4]

A second response is Hybrid Intelligent Testing, which combines Coverage-Directed Test Selection with Novelty-Driven Verification. In the cited paper, this hybrid approach is motivated by the observation that constrained random test generation alone can require very large numbers of tests; the hybrid method is described as addressing the limitations of the individual component methods to make testing both efficient and effective. [C5]

Example in processor verification

The provided processor-verification evidence gives a concrete example of constrained-random generation in practice. It describes RISC-V DV as using SystemVerilog together with UVM to continuously generate RISC-V instruction streams from constrained-random descriptions, with each instruction stream representing a test case. That source also states that RISC-V DV provides a high-level co-simulation interface based on execution log comparison and supports several ISA extensions as well as CSR testing. At the same time, it reports two disadvantages in that setting: restrictions added to avoid infinite loops and platform-dependent memory accesses, and significant performance overhead due to the framework's generic, fully decoupled test-generation and co-simulation structure. [C6]

The same case-study also situates constrained-random and constraint-oriented generation among related instruction-stream generation approaches, including model-based methods using constraint solving, an optimized framework that propagates constraints across multiple instructions, and a test-program generator whose coverage model contains constraints describing execution paths of individual instructions. [C7]