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STIMSMITH

Generic Simulation Testbench

CodeArtifact
First seen 6/10/2026
Last seen 6/10/2026
Evidence 5 chunks

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RELATIONSHIPS

9 connections
CocoTB uses → 98% 2e
The generic simulation testbench is implemented using the Cocotb Python verification framework.
Wishbone Bus Interface uses → 95% 2e
The testbench uses the Wishbone bus interface to communicate with the processor under test.
Spike (ISS) uses → 96% 2e
The testbench compares execution traces against the Spike reference model.
Fetch and Commit Trace Merging uses → 95% 2e
The testbench merges fetch and commit trace fragments into a final execution trace.
Speculative Fetch Detection uses → 93% 2e
The testbench detects and discards speculative fetches during trace construction.
reference model comparison uses → 97% 2e
The testbench compares processor execution traces against a reference model.
Execution Trace Generation uses → 96% 1e
The testbench monitors processor interfaces to generate execution traces for comparison.
Instruction Fetch Interface Monitoring uses → 96% 1e
The testbench monitors the instruction fetch interface to capture fetch events.
Register File Write Port Monitoring uses → 96% 1e
The testbench monitors register file write ports to detect commits.