Reusable Verification Environment for a RISC-V Vector Accelerator
PaperFirst seen 6/14/2026
Last seen 6/14/2026
Evidence 9 chunks
NEIGHBORHOOD
32 nodes · 50 edgesgraph · Reusable Verification Environment for a RISC-V Vector Accelerator · depth=1
RELATIONSHIPS
31 connectionsJosue Quiroga is listed as an author of the paper.
Roberto Ignacio Genovese is listed as an author of the paper.
Ivan Diaz is listed as an author of the paper.
Henrique Yano is listed as an author of the paper.
Asif Ali is listed as an author of the paper.
Nehir Sonmez is listed as an author of the paper.
Oscar Palomar is listed as an author of the paper.
Victor Jimenez is listed as a contributor/author affiliated with Semidynamics.
Mario Rodriguez is listed as a contributor/author affiliated with Codasip.
Marc Dominguez is listed as a contributor/author affiliated with Codasip.
The paper is produced by researchers from BSC.
The paper introduces a reusable verification environment for a RISC-V vector accelerator.
The paper uses UVM as the basis for the verification environment.
The verification environment performs co-simulation of vector instructions.
The paper uses RISCV-DV for random instruction generation in the verification environment.
The paper uses Spike as the ISA simulator reference model.
The paper uses GitLab CI for continuous integration pipelines.
The paper employs random instruction generation as a key testing strategy.
The paper implements functional coverage as part of the verification environment.
The paper describes a continuous integration environment for the verification infrastructure.
The paper uses polymorphism to enable reusability across different projects.
The paper uses OOP to foster reusability of modules across projects.
The paper uses SystemVerilog DPI to communicate with the Spike ISS.
The paper uses UVM factory override to swap ISS implementations.
The paper cites and discusses the hybrid verification solution paper by C. Li et al.
The paper cites Testbench Flexibility as a Foundation for Success as related work.
UVM-based Verification of a RISC-V Processor Core Using a Golden Predictor Model (Zachariasova et al.) mentions → 100% 1e
The paper cites the UVM-based verification paper by Zachariasova et al.
The paper introduces vpu-dv as the base interface-agnostic verification environment.
The paper introduces epac-vpu-dv as the EPI-specific verification environment.
The paper introduces eprocessor-vpu-dv as the eProcessor-specific verification environment.
The paper introduces epac2-vpu-dv as the second-generation EPI vector unit verification environment.