Creating Verification Environment Using RISCV-DV With Open and Closed Source Tools
PaperFirst seen 6/8/2026
Last seen 6/8/2026
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12 connectionsThe paper is authored by Deniz Zakir Eroğlu.
The paper is authored by Mete Kaan Özden.
The paper was published by IEEE.
The paper introduces a reusable verification framework combining RISCV-DV with open and closed source tools.
The paper uses RISCV-DV as the main random instruction generator in the verification framework.
The paper uses Spike ISS as an open-source reference simulator.
The paper uses Xcelium as the commercial simulation tool.
The paper applies the verification framework to the Hornet RV32IMF core.
The paper employs random instruction generation via RISCV-DV to detect subtle verification bugs.
The paper uses structured CSV-based scripts to compare execution logs between the core under test and Spike.
The paper integrates a custom tracer into the Hornet core to capture execution logs.
The paper evaluates compliance with IEEE-754 rounding modes and precision in arithmetic units.