Hornet RV32IMF core

Tool

The Hornet RV32IMF core is a RISC-V processor implementing the RV32IMF instruction set profile (32-bit base integer with multiplication/division and floating-point extensions) along with IEEE-754 floating-point arithmetic. It integrates a custom tracer for execution log capture and has been used as the design under test in a reusable verification framework based on RISCV-DV.

First seen 6/8/2026

Last seen 6/8/2026

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Hornet RV32IMF core

Overview

The Hornet RV32IMF core is a RISC-V processor that implements the RV32IMF instruction set architecture profile, combining a 32-bit base integer ISA (RV32I), the integer multiplication and division extension (M), and the single-precision floating-point extension (F). It also implements the IEEE-754 floating-point arithmetic standard, including operations such as division and square root in its arithmetic units.

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RELATIONSHIPS

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Creating Verification Environment Using RISCV-DV With Open and Closed Source Tools ← uses 100% 1e

The paper applies the verification framework to the Hornet RV32IMF core.

RISC-V ISA implements → 95% 1e

The Hornet RV32IMF core is a processor implementing the RISC-V ISA.

IEEE-754 implements → 90% 1e

The Hornet RV32IMF core implements IEEE-754 floating-point arithmetic.

custom tracer for execution log capture uses → 95% 1e

The custom tracer is integrated into the Hornet RV32IMF core to capture execution logs.

LINKED ENTITIES

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Creating Verification Environment Using RISCV-DV With Open and Closed Source Tools USES Extracted graph relationship

RISC-V ISA IMPLEMENTS Extracted graph relationship

IEEE-754 IMPLEMENTS Extracted graph relationship

custom tracer for execution log capture USES Extracted graph relationship

CITATIONS

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5 citations — click to expand

[1] Hornet is an RV32IMF core whose verification is described in the ISMSIT 2025 paper 'Creating Verification Environment Using RISCV-DV With Open and Closed Source Tools'. Creating Verification Environment Using RISCV-DV With Open and Closed Source Tools (ISMSIT 2025)

[2] A custom tracer integrated into the Hornet RV32IMF core captures execution logs, which are automatically compared with Spike through structured CSV-based scripts. Creating Verification Environment Using RISCV-DV With Open and Closed Source Tools (ISMSIT 2025)

[3] The verification framework uses RISCV-DV for random instruction generation and combines open-source (Python flow, Spike ISS) and commercial (Xcelium) tools. Creating Verification Environment Using RISCV-DV With Open and Closed Source Tools (ISMSIT 2025)

[4] The framework uncovered and resolved multiple floating-point bugs in Hornet, including incorrect handling of IEEE-754 rounding modes and precision loss in division and square root arithmetic units. Creating Verification Environment Using RISCV-DV With Open and Closed Source Tools (ISMSIT 2025)

[5] The verification approach ensures compliance of the core with both the RISC-V and IEEE-754 standards. Creating Verification Environment Using RISCV-DV With Open and Closed Source Tools (ISMSIT 2025)