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Hornet RV32IMF core

Tool WIKI v1 · 6/8/2026

The Hornet RV32IMF core is a RISC-V processor implementing the RV32IMF instruction set profile (32-bit base integer with multiplication/division and floating-point extensions) along with IEEE-754 floating-point arithmetic. It integrates a custom tracer for execution log capture and has been used as the design under test in a reusable verification framework based on RISCV-DV.

Hornet RV32IMF core

Overview

The Hornet RV32IMF core is a RISC-V processor that implements the RV32IMF instruction set architecture profile, combining a 32-bit base integer ISA (RV32I), the integer multiplication and division extension (M), and the single-precision floating-point extension (F). It also implements the IEEE-754 floating-point arithmetic standard, including operations such as division and square root in its arithmetic units.

Architecture and ISA support

  • RISC-V ISA profile: RV32IMF (32-bit integer base + M extension + F extension).
  • Floating-point arithmetic: Conforms to the IEEE-754 standard, supporting operations that include division and square root, which are subject to rounding-mode and precision-loss considerations.

Custom tracer for execution log capture

Hornet integrates a custom tracer that captures execution logs during simulation. The tracer's output is automatically compared against the Spike RISC-V instruction set simulator (ISS) using structured CSV-based comparison scripts. This tracer/log-comparison mechanism is what makes the core amenable to randomized, framework-driven verification rather than purely directed testing.

Verification experience

In the ISMSIT 2025 paper by Eroğlu, Özden, and Örs, Hornet is the design under verification for a reusable framework that combines RISCV-DV for random instruction generation with both open-source tooling (a Python flow and Spike ISS) and commercial tooling (Xcelium). Using this framework, the authors:

  • Systematically exercised Hornet with randomized instruction streams.
  • Detected subtle errors that directed tests typically miss.
  • Uncovered and resolved multiple floating-point bugs in Hornet, including:
    • Incorrect handling of IEEE-754 rounding modes.
    • Precision loss in arithmetic units such as division and square root.
  • Confirmed compliance of the core with both the RISC-V ISA and the IEEE-754 standard.

The framework's ability to run against both open-source and closed-source simulation flows (Spike/Python vs. Xcelium) demonstrates that the custom tracer and CSV-based comparison approach used with Hornet is portable across vendor toolchains.

Standards and compliance

  • RISC-V conformance (RV32IMF profile).
  • IEEE-754 conformance for floating-point operations, including proper handling of rounding modes and precision in division/square-root units.

LINKED ENTITIES

4 links
Creating Verification Environment Using RISCV-DV With Open and Closed Source Tools USES
RISC-V ISA IMPLEMENTS
IEEE-754 IMPLEMENTS
custom tracer for execution log capture USES

CITATIONS

5 sources
5 citations
[1] Hornet is an RV32IMF core whose verification is described in the ISMSIT 2025 paper 'Creating Verification Environment Using RISCV-DV With Open and Closed Source Tools'. Creating Verification Environment Using RISCV-DV With Open and Closed Source Tools (ISMSIT 2025)
[2] A custom tracer integrated into the Hornet RV32IMF core captures execution logs, which are automatically compared with Spike through structured CSV-based scripts. Creating Verification Environment Using RISCV-DV With Open and Closed Source Tools (ISMSIT 2025)
[3] The verification framework uses RISCV-DV for random instruction generation and combines open-source (Python flow, Spike ISS) and commercial (Xcelium) tools. Creating Verification Environment Using RISCV-DV With Open and Closed Source Tools (ISMSIT 2025)
[4] The framework uncovered and resolved multiple floating-point bugs in Hornet, including incorrect handling of IEEE-754 rounding modes and precision loss in division and square root arithmetic units. Creating Verification Environment Using RISCV-DV With Open and Closed Source Tools (ISMSIT 2025)
[5] The verification approach ensures compliance of the core with both the RISC-V and IEEE-754 standards. Creating Verification Environment Using RISCV-DV With Open and Closed Source Tools (ISMSIT 2025)