Chisel — STIMSMITH

Chisel (Hardware Construction Language)

Concept

Chisel (Constructing Hardware In a Scala Embedded Language) is a Scala-embedded hardware construction language that describes circuits as parameterized generators. It brings object-oriented and functional programming, type safety, and parameterization to hardware design while targeting synthesizable RTL, and is widely adopted in the RISC-V ecosystem for cores such as Rocket and BOOM. Chisel-generated designs flow through the FIRRTL intermediate representation and CIRCT MLIR compiler infrastructure, which enables downstream tooling for verification, coverage instrumentation, and debugging.

First seen 5/29/2026

Last seen 7/10/2026

Evidence 6 chunks

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WIKI

Overview

Chisel (Constructing Hardware In a Scala Embedded Language) is a Scala-embedded hardware construction language that describes circuits as parameterized generators rather than fixed RTL instances [HiFuzz paper]. By being embedded in Scala, Chisel brings object-oriented and functional programming, type safety, and parameterization to hardware design, while still targeting synthesizable RTL [Tywaves paper].

Language Features and Design Philosophy

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NEIGHBORHOOD

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RELATIONSHIPS

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DejaVuzz ← uses 85% 1e

DejaVuzz treats all register arrays generated by Chisel Vec constructor as potential sinks.

LINKED ENTITIES

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FIRRTL intermediate representation emitted by Chisel that supports compiler passes MorFuzz implemented a FIRRTL pass to instrument control registers, and Laeufer et al. describe FIRRTL-based coverage instrumentation passes relevant to Chisel designs.

Rocket RISC-V processor implemented in Chisel Multiple sources explicitly identify Rocket as a five-stage, single-issue, in-order RISC-V processor written in Chisel.

BOOM RISC-V out-of-order processor implemented in Chisel Multiple sources explicitly identify BOOM as the third-generation Berkeley out-of-order RISC-V processor written in Chisel.

CITATIONS

12 sources

12 citations — click to expand

[1] Chisel is a Scala-embedded hardware construction language that describes circuits as parameterized generators rather than fixed RTL instances. HiFuzz: Hierarchical Reinforcement Learning for Semantic-Aware and Adaptive CPU Fuzzing

[2] Chisel brings object-oriented and functional programming, type safety, and parameterization to hardware design. Tywaves: A Typed Waveform Viewer for Chisel

[3] Chisel designs can flow through the CIRCT MLIR compiler, which preserves higher-level type information lost in translation to Verilog. Tywaves: A Typed Waveform Viewer for Chisel

[4] Chisel provides a blackbox mechanism for instantiating external modules, used by ChiselVerify to remain HDL-agnostic at the verification boundary. Open-Source Verification with Chisel and Scala

[5] Rocket is a five-stage, single-issue, in-order scalar RISC-V processor written in Chisel; the first RISC-V processor open-sourced by UC Berkeley; actively supports hypervisor and cryptography extensions. MorFuzz: Fuzzing Processor via Runtime Instruction Morphing enhanced Synchronizable Co-simulation

[6] BOOM is the third-generation Berkeley Out-of-Order Machine, written in Chisel; out-of-order superscalar; verified on FPGA. MorFuzz: Fuzzing Processor via Runtime Instruction Morphing enhanced Synchronizable Co-simulation

[7] DejaVuzz treats all register arrays, including those generated by the Chisel Vec constructor, as potential sinks for diffIFT instrumentation. DejaVuzz: Disclosing Transient Execution Bugs with Dynamic Swappable Memory and Differential Information Flow Tracking Assisted Processor Fuzzing

[8] MorFuzz implemented a FIRRTL pass to instrument all control registers for control-register coverage on Chisel-written DUTs. MorFuzz: Fuzzing Processor via Runtime Instruction Morphing enhanced Synchronizable Co-simulation

[9] HiFuzz treats Rocket and BOOM as Chisel-based DUTs and uses high-level coverage structure from Chisel/FIRRTL when available, while also evaluating the SystemVerilog-based CVA6. HiFuzz: Hierarchical Reinforcement Learning for Semantic-Aware and Adaptive CPU Fuzzing

[10] Laeufer et al. show that line, toggle, and FSM coverage can be implemented as compiler-instrumentation passes over FIRRTL, decoupling coverage from a specific simulator backend. HiFuzz: Hierarchical Reinforcement Learning for Semantic-Aware and Adaptive CPU Fuzzing

[11] ChiselVerify is an open-source verification framework on top of Chisel and Scala that exposes functional coverage, constrained-random verification, bus functional models, and transaction-level modeling. Open-Source Verification with Chisel and Scala

[12] Tywaves introduces a typed waveform format bridging Chisel source-level types into the Surfer waveform viewer, with contributions to the Chisel library and CIRCT MLIR compiler. Tywaves: A Typed Waveform Viewer for Chisel