Chisel — STIMSMITH

Chisel (Hardware Construction Language)

Concept

Chisel (Constructing Hardware In a Scala Embedded Language) is a broadly adopted hardware description and construction language that embeds hardware design inside the Scala programming language, bringing object-oriented and functional programming, type safety, and parameterization to hardware design. It is used to implement notable open-source RISC-V processors such as Rocket and BOOM, and serves as a foundation for downstream tooling like ChiselVerify and DejaVuzz.

First seen 5/29/2026

Last seen 6/13/2026

Evidence 3 chunks

Wiki v1

WIKI

Overview

Chisel (Constructing Hardware In a Scala Embedded Language) is a broadly adopted hardware description language (HDL) that embeds hardware design inside the Scala programming language [Tywaves paper]. By being embedded in Scala, Chisel brings object-oriented and functional programming, type safety, and parameterization to hardware design, while still targeting synthesizable RTL.

Language Features and Design Philosophy

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NEIGHBORHOOD

2 nodes · 1 edges

graph · Chisel · depth=1

RELATIONSHIPS

1 connections

DejaVuzz ← uses 85% 1e

DejaVuzz treats all register arrays generated by Chisel Vec constructor as potential sinks.

LINKED ENTITIES

1 links

DejaVuzz USES Extracted graph relationship

CITATIONS

10 sources

10 citations — click to expand

[1] Chisel stands for Constructing Hardware In a Scala Embedded Language and is a broadly adopted HDL. Tywaves: A Typed Waveform Viewer for Chisel

[2] Chisel brings object-oriented and functional programming, type-safety, and parameterization to hardware design. Tywaves: A Typed Waveform Viewer for Chisel

[3] Tywaves makes contributions to the Chisel library and CIRCT MLIR compiler to support typed waveforms. Tywaves: A Typed Waveform Viewer for Chisel

[4] ChiselVerify is an open-source verification framework built on top of Chisel and Scala, using Chisel blackboxes to be HDL-agnostic. Open-Source Verification with Chisel and Scala

[5] ChiselVerify provides SystemVerilog-inspired features such as functional coverage, constrained-random verification, bus functional models, and transaction-level modeling. Open-Source Verification with Chisel and Scala

[6] Rocket is a five-stage, single-issue, in-order scalar RISC-V processor written in Chisel. MorFuzz: Fuzzing Processor via Runtime Instruction Morphing enhanced Synchronizable Co-simulation

[7] BOOM (Berkeley Out-of-Order Machine) is a third-generation out-of-order superscalar RISC-V processor written in Chisel. MorFuzz: Fuzzing Processor via Runtime Instruction Morphing enhanced Synchronizable Co-simulation

[8] DejaVuzz treats register arrays generated by the Chisel Vec constructor as potential sinks by default. DejaVuzz: Disclosing Transient Execution Bugs with Dynamic Swappable Memory and Differential Information Flow Tracking Assisted Processor Fuzzing

[9] DejaVuzz evaluates Chisel-written cores BOOM and XiangShan. DejaVuzz: Disclosing Transient Execution Bugs with Dynamic Swappable Memory and Differential Information Flow Tracking Assisted Processor Fuzzing

[10] Chisel designs lose type information and data-structure hierarchies when translated to Verilog, simulated, and viewed in waveform viewers. Tywaves: A Typed Waveform Viewer for Chisel